Lines Matching refs:isPPC64
95 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
614 if (!(Subtarget.isPPC64() && Subtarget.hasP9Vector() && in shouldReduceRegisterPressure()
672 assert((Subtarget.isPPC64() && Subtarget.hasP9Vector() && in generateLoadForNewConst()
1265 bool isPPC64 = Subtarget.isPPC64(); in analyzeBranch() local
1331 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1342 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1399 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1413 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1479 bool isPPC64 = Subtarget.isPPC64(); in insertBranch() local
1487 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
1488 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
1504 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
1505 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
2100 bool isPPC64 = Subtarget.isPPC64(); in onlyFoldImmediate() local
2101 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2182 bool isPPC64 = Subtarget.isPPC64(); in PredicateInstruction() local
2183 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) in PredicateInstruction()
2184 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); in PredicateInstruction()
2205 bool isPPC64 = Subtarget.isPPC64(); in PredicateInstruction() local
2206 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in PredicateInstruction()
2207 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); in PredicateInstruction()
2248 bool isPPC64 = Subtarget.isPPC64(); in PredicateInstruction() local
2251 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) in PredicateInstruction()
2255 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) in PredicateInstruction()
2259 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) in PredicateInstruction()
2269 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::Implicit) in PredicateInstruction()
2270 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine); in PredicateInstruction()
2401 bool isPPC64 = Subtarget.isPPC64(); in optimizeCompareInstr() local
2417 if (isPPC64) { in optimizeCompareInstr()
2788 if (Subtarget.isPPC64() && Opc == PPC::CMPWI) in optimizeCmpPostRA()
3111 const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008; in expandPostRAPseudo()
3112 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; in expandPostRAPseudo()
3113 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); in expandPostRAPseudo()
3123 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; in expandPostRAPseudo()
3131 bool Is64 = Subtarget.isPPC64(); in expandPostRAPseudo()
3235 unsigned CmpOp = Subtarget.isPPC64() ? PPC::CMPD : PPC::CMPW; in expandPostRAPseudo()
3360 bool isPPC64 = Subtarget.isPPC64(); in materializeImmPostRA() local
3365 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LI8 : PPC::LI), Reg).addImm(Imm); in materializeImmPostRA()
3367 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LIS8 : PPC::LIS), Reg) in materializeImmPostRA()
3370 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::ORI8 : PPC::ORI), Reg) in materializeImmPostRA()
3374 assert(isPPC64 && "Materializing 64-bit immediate to single register is " in materializeImmPostRA()
5234 Register SPReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in isTOCSaveMI()
5419 return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ)); in isBDNZ()
5456 MF->getSubtarget<PPCSubtarget>().isPPC64() ? PPC::CTR8 : PPC::CTR, in createTripCountGreaterCondition()
5516 unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop); in findLoopInstr()