Lines Matching full:ppc
15 #include "PPC.h"
48 #define DEBUG_TYPE "ppc-instr-info"
67 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
70 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
73 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
78 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
82 FMARPFactor("ppc-fma-rp-factor", cl::Hidden, cl::init(1.5),
86 "ppc-fma-rp-reduction", cl::Hidden, cl::init(true),
93 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, in PPCInstrInfo()
95 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
105 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
106 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
124 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
128 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
129 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
184 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
185 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
187 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
188 PPC::CRBITRCRegClass.contains(Reg); in getOperandLatency()
200 case PPC::DIR_7400: in getOperandLatency()
201 case PPC::DIR_750: in getOperandLatency()
202 case PPC::DIR_970: in getOperandLatency()
203 case PPC::DIR_E5500: in getOperandLatency()
204 case PPC::DIR_PWR4: in getOperandLatency()
205 case PPC::DIR_PWR5: in getOperandLatency()
206 case PPC::DIR_PWR5X: in getOperandLatency()
207 case PPC::DIR_PWR6: in getOperandLatency()
208 case PPC::DIR_PWR6X: in getOperandLatency()
209 case PPC::DIR_PWR7: in getOperandLatency()
210 case PPC::DIR_PWR8: in getOperandLatency()
240 case PPC::FADD: in isAssociativeAndCommutative()
241 case PPC::FADDS: in isAssociativeAndCommutative()
243 case PPC::FMUL: in isAssociativeAndCommutative()
244 case PPC::FMULS: in isAssociativeAndCommutative()
246 case PPC::VADDFP: in isAssociativeAndCommutative()
248 case PPC::XSADDDP: in isAssociativeAndCommutative()
249 case PPC::XVADDDP: in isAssociativeAndCommutative()
250 case PPC::XVADDSP: in isAssociativeAndCommutative()
251 case PPC::XSADDSP: in isAssociativeAndCommutative()
253 case PPC::XSMULDP: in isAssociativeAndCommutative()
254 case PPC::XVMULDP: in isAssociativeAndCommutative()
255 case PPC::XVMULSP: in isAssociativeAndCommutative()
256 case PPC::XSMULSP: in isAssociativeAndCommutative()
261 case PPC::MULHD: in isAssociativeAndCommutative()
262 case PPC::MULLD: in isAssociativeAndCommutative()
263 case PPC::MULHW: in isAssociativeAndCommutative()
264 case PPC::MULLW: in isAssociativeAndCommutative()
287 {PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2, PPC::XSSUBDP},
288 {PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2, PPC::XSSUBSP},
289 {PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC::XVSUBDP},
290 {PPC::XVMADDASP, PPC::XVADDSP, PPC::XVMULSP, 1, 2, PPC::XVSUBSP},
291 {PPC::FMADD, PPC::FADD, PPC::FMUL, 3, 1, PPC::FSUB},
292 {PPC::FMADDS, PPC::FADDS, PPC::FMULS, 3, 1, PPC::FSUBS}};
435 if (Opcode != PPC::XSMADDASP && Opcode != PPC::XSMADDADP) in getFMAPatterns()
574 // Record the placeholder PPC::ZERO8 we add in reassociateFMA. in finalizeInsInstrs()
578 if (Operand.getReg() == PPC::ZERO8) { in finalizeInsInstrs()
609 // %7:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0, in shouldReduceRegisterPressure()
649 *MBB->getParent(), PPC::RegisterPressureSets::VSSRC); in shouldReduceRegisterPressure()
652 return GetMBBPressure(MBB)[PPC::RegisterPressureSets::VSSRC] > in shouldReduceRegisterPressure()
680 Register VReg1 = MRI->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass); in generateLoadForNewConst()
682 BuildMI(*MF, MI->getDebugLoc(), get(PPC::ADDIStocHA8), VReg1) in generateLoadForNewConst()
683 .addReg(PPC::X2) in generateLoadForNewConst()
692 LoadOpcode = PPC::DFLOADf32; in generateLoadForNewConst()
694 LoadOpcode = PPC::DFLOADf64; in generateLoadForNewConst()
1016 .addReg(PPC::ZERO8); in reassociateFMA()
1053 case PPC::EXTSW: in isCoalescableExtInstr()
1054 case PPC::EXTSW_32: in isCoalescableExtInstr()
1055 case PPC::EXTSW_32_64: in isCoalescableExtInstr()
1058 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
1085 case PPC::LI: in isReallyTriviallyReMaterializable()
1086 case PPC::LI8: in isReallyTriviallyReMaterializable()
1087 case PPC::PLI: in isReallyTriviallyReMaterializable()
1088 case PPC::PLI8: in isReallyTriviallyReMaterializable()
1089 case PPC::LIS: in isReallyTriviallyReMaterializable()
1090 case PPC::LIS8: in isReallyTriviallyReMaterializable()
1091 case PPC::ADDIStocHA: in isReallyTriviallyReMaterializable()
1092 case PPC::ADDIStocHA8: in isReallyTriviallyReMaterializable()
1093 case PPC::ADDItocL: in isReallyTriviallyReMaterializable()
1094 case PPC::ADDItocL8: in isReallyTriviallyReMaterializable()
1095 case PPC::LOAD_STACK_GUARD: in isReallyTriviallyReMaterializable()
1096 case PPC::PPCLdFixedAddr: in isReallyTriviallyReMaterializable()
1097 case PPC::XXLXORz: in isReallyTriviallyReMaterializable()
1098 case PPC::XXLXORspz: in isReallyTriviallyReMaterializable()
1099 case PPC::XXLXORdpz: in isReallyTriviallyReMaterializable()
1100 case PPC::XXLEQVOnes: in isReallyTriviallyReMaterializable()
1101 case PPC::XXSPLTI32DX: in isReallyTriviallyReMaterializable()
1102 case PPC::XXSPLTIW: in isReallyTriviallyReMaterializable()
1103 case PPC::XXSPLTIDP: in isReallyTriviallyReMaterializable()
1104 case PPC::V_SET0B: in isReallyTriviallyReMaterializable()
1105 case PPC::V_SET0H: in isReallyTriviallyReMaterializable()
1106 case PPC::V_SET0: in isReallyTriviallyReMaterializable()
1107 case PPC::V_SETALLONESB: in isReallyTriviallyReMaterializable()
1108 case PPC::V_SETALLONESH: in isReallyTriviallyReMaterializable()
1109 case PPC::V_SETALLONES: in isReallyTriviallyReMaterializable()
1110 case PPC::CRSET: in isReallyTriviallyReMaterializable()
1111 case PPC::CRUNSET: in isReallyTriviallyReMaterializable()
1112 case PPC::XXSETACCZ: in isReallyTriviallyReMaterializable()
1113 case PPC::XXSETACCZW: in isReallyTriviallyReMaterializable()
1137 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMI_rec) in commuteInstructionImpl()
1140 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because in commuteInstructionImpl()
1222 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode()); in findCommutedOpIndices()
1238 default: Opcode = PPC::NOP; break; in insertNoop()
1239 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; in insertNoop()
1240 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
1241 …case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling mod… in insertNoop()
1243 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
1253 Nop.setOpcode(PPC::NOP); in getNop()
1278 if (I->getOpcode() == PPC::B && in analyzeBranch()
1294 if (LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1299 } else if (LastInst.getOpcode() == PPC::BCC) { in analyzeBranch()
1307 } else if (LastInst.getOpcode() == PPC::BC) { in analyzeBranch()
1312 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
1315 } else if (LastInst.getOpcode() == PPC::BCn) { in analyzeBranch()
1320 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
1323 } else if (LastInst.getOpcode() == PPC::BDNZ8 || in analyzeBranch()
1324 LastInst.getOpcode() == PPC::BDNZ) { in analyzeBranch()
1331 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1334 } else if (LastInst.getOpcode() == PPC::BDZ8 || in analyzeBranch()
1335 LastInst.getOpcode() == PPC::BDZ) { in analyzeBranch()
1342 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1358 // If the block ends with PPC::B and PPC:BCC, handle it. in analyzeBranch()
1359 if (SecondLastInst.getOpcode() == PPC::BCC && in analyzeBranch()
1360 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1369 } else if (SecondLastInst.getOpcode() == PPC::BC && in analyzeBranch()
1370 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1375 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
1379 } else if (SecondLastInst.getOpcode() == PPC::BCn && in analyzeBranch()
1380 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1385 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
1389 } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 || in analyzeBranch()
1390 SecondLastInst.getOpcode() == PPC::BDNZ) && in analyzeBranch()
1391 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1399 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1403 } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 || in analyzeBranch()
1404 SecondLastInst.getOpcode() == PPC::BDZ) && in analyzeBranch()
1405 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1413 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1419 // If the block ends with two PPC:Bs, handle it. The second one is not in analyzeBranch()
1421 if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1443 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC && in removeBranch()
1444 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in removeBranch()
1445 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in removeBranch()
1446 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in removeBranch()
1456 if (I->getOpcode() != PPC::BCC && in removeBranch()
1457 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in removeBranch()
1458 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in removeBranch()
1459 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in removeBranch()
1476 "PPC branch conditions have two components!"); in insertBranch()
1484 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); in insertBranch()
1485 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
1487 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
1488 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
1489 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in insertBranch()
1490 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); in insertBranch()
1491 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in insertBranch()
1492 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); in insertBranch()
1494 BuildMI(&MBB, DL, get(PPC::BCC)) in insertBranch()
1502 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
1504 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
1505 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
1506 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in insertBranch()
1507 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); in insertBranch()
1508 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in insertBranch()
1509 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); in insertBranch()
1511 BuildMI(&MBB, DL, get(PPC::BCC)) in insertBranch()
1515 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); in insertBranch()
1533 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in canInsertSelect()
1549 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1550 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1551 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1552 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1572 "PPC branch conditions have two components!"); in insertSelect()
1580 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
1581 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
1583 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1584 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
1587 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL; in insertSelect()
1588 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm()); in insertSelect()
1593 case PPC::PRED_EQ: in insertSelect()
1594 case PPC::PRED_EQ_MINUS: in insertSelect()
1595 case PPC::PRED_EQ_PLUS: in insertSelect()
1596 SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
1597 case PPC::PRED_NE: in insertSelect()
1598 case PPC::PRED_NE_MINUS: in insertSelect()
1599 case PPC::PRED_NE_PLUS: in insertSelect()
1600 SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
1601 case PPC::PRED_LT: in insertSelect()
1602 case PPC::PRED_LT_MINUS: in insertSelect()
1603 case PPC::PRED_LT_PLUS: in insertSelect()
1604 SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
1605 case PPC::PRED_GE: in insertSelect()
1606 case PPC::PRED_GE_MINUS: in insertSelect()
1607 case PPC::PRED_GE_PLUS: in insertSelect()
1608 SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
1609 case PPC::PRED_GT: in insertSelect()
1610 case PPC::PRED_GT_MINUS: in insertSelect()
1611 case PPC::PRED_GT_PLUS: in insertSelect()
1612 SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
1613 case PPC::PRED_LE: in insertSelect()
1614 case PPC::PRED_LE_MINUS: in insertSelect()
1615 case PPC::PRED_LE_PLUS: in insertSelect()
1616 SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
1617 case PPC::PRED_UN: in insertSelect()
1618 case PPC::PRED_UN_MINUS: in insertSelect()
1619 case PPC::PRED_UN_PLUS: in insertSelect()
1620 SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
1621 case PPC::PRED_NU: in insertSelect()
1622 case PPC::PRED_NU_MINUS: in insertSelect()
1623 case PPC::PRED_NU_PLUS: in insertSelect()
1624 SubIdx = PPC::sub_un; SwapOps = true; break; in insertSelect()
1625 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break; in insertSelect()
1626 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break; in insertSelect()
1635 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
1636 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
1638 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
1639 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass; in insertSelect()
1653 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT || in getCRBitValue()
1654 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT || in getCRBitValue()
1655 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT || in getCRBitValue()
1656 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT) in getCRBitValue()
1658 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT || in getCRBitValue()
1659 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT || in getCRBitValue()
1660 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT || in getCRBitValue()
1661 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT) in getCRBitValue()
1663 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ || in getCRBitValue()
1664 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ || in getCRBitValue()
1665 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ || in getCRBitValue()
1666 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ) in getCRBitValue()
1668 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN || in getCRBitValue()
1669 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN || in getCRBitValue()
1670 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN || in getCRBitValue()
1671 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN) in getCRBitValue()
1685 if (PPC::F8RCRegClass.contains(DestReg) && in copyPhysReg()
1686 PPC::VSRCRegClass.contains(SrcReg)) { in copyPhysReg()
1688 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
1694 } else if (PPC::F8RCRegClass.contains(SrcReg) && in copyPhysReg()
1695 PPC::VSRCRegClass.contains(DestReg)) { in copyPhysReg()
1697 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
1706 if (PPC::CRBITRCRegClass.contains(SrcReg) && in copyPhysReg()
1707 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
1709 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); in copyPhysReg()
1713 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg) in copyPhysReg()
1719 } else if (PPC::CRRCRegClass.contains(SrcReg) && in copyPhysReg()
1720 (PPC::G8RCRegClass.contains(DestReg) || in copyPhysReg()
1721 PPC::GPRCRegClass.contains(DestReg))) { in copyPhysReg()
1722 bool Is64Bit = PPC::G8RCRegClass.contains(DestReg); in copyPhysReg()
1723 unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF; in copyPhysReg()
1724 unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM; in copyPhysReg()
1737 } else if (PPC::G8RCRegClass.contains(SrcReg) && in copyPhysReg()
1738 PPC::VSFRCRegClass.contains(DestReg)) { in copyPhysReg()
1741 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg); in copyPhysReg()
1745 } else if (PPC::VSFRCRegClass.contains(SrcReg) && in copyPhysReg()
1746 PPC::G8RCRegClass.contains(DestReg)) { in copyPhysReg()
1749 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg); in copyPhysReg()
1752 } else if (PPC::SPERCRegClass.contains(SrcReg) && in copyPhysReg()
1753 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
1754 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg); in copyPhysReg()
1757 } else if (PPC::GPRCRegClass.contains(SrcReg) && in copyPhysReg()
1758 PPC::SPERCRegClass.contains(DestReg)) { in copyPhysReg()
1759 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg); in copyPhysReg()
1765 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1766 Opc = PPC::OR; in copyPhysReg()
1767 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1768 Opc = PPC::OR8; in copyPhysReg()
1769 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1770 Opc = PPC::FMR; in copyPhysReg()
1771 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1772 Opc = PPC::MCRF; in copyPhysReg()
1773 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1774 Opc = PPC::VOR; in copyPhysReg()
1775 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1784 Opc = PPC::XXLOR; in copyPhysReg()
1785 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) || in copyPhysReg()
1786 PPC::VSSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1787 Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf; in copyPhysReg()
1789 PPC::VSRpRCRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
1790 if (SrcReg > PPC::VSRp15) in copyPhysReg()
1791 SrcReg = PPC::V0 + (SrcReg - PPC::VSRp16) * 2; in copyPhysReg()
1793 SrcReg = PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2; in copyPhysReg()
1794 if (DestReg > PPC::VSRp15) in copyPhysReg()
1795 DestReg = PPC::V0 + (DestReg - PPC::VSRp16) * 2; in copyPhysReg()
1797 DestReg = PPC::VSL0 + (DestReg - PPC::VSRp0) * 2; in copyPhysReg()
1798 BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg). in copyPhysReg()
1800 BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg + 1). in copyPhysReg()
1804 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1805 Opc = PPC::CROR; in copyPhysReg()
1806 else if (PPC::SPERCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1807 Opc = PPC::EVOR; in copyPhysReg()
1808 else if ((PPC::ACCRCRegClass.contains(DestReg) || in copyPhysReg()
1809 PPC::UACCRCRegClass.contains(DestReg)) && in copyPhysReg()
1810 (PPC::ACCRCRegClass.contains(SrcReg) || in copyPhysReg()
1811 PPC::UACCRCRegClass.contains(SrcReg))) { in copyPhysReg()
1817 bool DestPrimed = PPC::ACCRCRegClass.contains(DestReg); in copyPhysReg()
1818 bool SrcPrimed = PPC::ACCRCRegClass.contains(SrcReg); in copyPhysReg()
1820 PPC::VSL0 + (SrcReg - (SrcPrimed ? PPC::ACC0 : PPC::UACC0)) * 4; in copyPhysReg()
1822 PPC::VSL0 + (DestReg - (DestPrimed ? PPC::ACC0 : PPC::UACC0)) * 4; in copyPhysReg()
1824 BuildMI(MBB, I, DL, get(PPC::XXMFACC), SrcReg).addReg(SrcReg); in copyPhysReg()
1826 BuildMI(MBB, I, DL, get(PPC::XXLOR), VSLDestReg + Idx) in copyPhysReg()
1830 BuildMI(MBB, I, DL, get(PPC::XXMTACC), DestReg).addReg(DestReg); in copyPhysReg()
1832 BuildMI(MBB, I, DL, get(PPC::XXMTACC), SrcReg).addReg(SrcReg); in copyPhysReg()
1834 } else if (PPC::G8pRCRegClass.contains(DestReg) && in copyPhysReg()
1835 PPC::G8pRCRegClass.contains(SrcReg)) { in copyPhysReg()
1837 unsigned DestRegIdx = DestReg - PPC::G8p0; in copyPhysReg()
1838 MCRegister DestRegSub0 = PPC::X0 + 2 * DestRegIdx; in copyPhysReg()
1839 MCRegister DestRegSub1 = PPC::X0 + 2 * DestRegIdx + 1; in copyPhysReg()
1840 unsigned SrcRegIdx = SrcReg - PPC::G8p0; in copyPhysReg()
1841 MCRegister SrcRegSub0 = PPC::X0 + 2 * SrcRegIdx; in copyPhysReg()
1842 MCRegister SrcRegSub1 = PPC::X0 + 2 * SrcRegIdx + 1; in copyPhysReg()
1843 BuildMI(MBB, I, DL, get(PPC::OR8), DestRegSub0) in copyPhysReg()
1846 BuildMI(MBB, I, DL, get(PPC::OR8), DestRegSub1) in copyPhysReg()
1864 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1865 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1867 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1868 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1870 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1872 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1874 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1876 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1878 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1880 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1882 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1884 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1886 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1888 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1890 } else if (PPC::ACCRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1894 } else if (PPC::UACCRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1898 } else if (PPC::WACCRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1902 } else if (PPC::VSRpRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1906 } else if (PPC::G8pRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1940 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
1941 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in StoreRegToStackSlot()
2035 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); in reverseBranchCondition()
2036 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) in reverseBranchCondition()
2040 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); in reverseBranchCondition()
2045 // This function performs that fold by replacing the operand with PPC::ZERO,
2051 if (DefOpc != PPC::LI && DefOpc != PPC::LI8) in onlyFoldImmediate()
2087 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && in onlyFoldImmediate()
2088 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) in onlyFoldImmediate()
2101 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2103 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2104 PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2128 if (MI.definesRegister(PPC::CTR, /*TRI=*/nullptr) || in MBBDefinesCTR()
2129 MI.definesRegister(PPC::CTR8, /*TRI=*/nullptr)) in MBBDefinesCTR()
2168 // TODO: Model FPSCR in PPC instruction definitions and remove the workaround in isSchedulingBoundary()
2169 case PPC::MFFS: in isSchedulingBoundary()
2170 case PPC::MTFSF: in isSchedulingBoundary()
2171 case PPC::FENCE: in isSchedulingBoundary()
2180 if (OpC == PPC::BLR || OpC == PPC::BLR8) { in PredicateInstruction()
2181 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
2183 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) in PredicateInstruction()
2184 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); in PredicateInstruction()
2189 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2190 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
2192 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2193 MI.setDesc(get(PPC::BCLRn)); in PredicateInstruction()
2196 MI.setDesc(get(PPC::BCCLR)); in PredicateInstruction()
2203 } else if (OpC == PPC::B) { in PredicateInstruction()
2204 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
2206 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in PredicateInstruction()
2207 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); in PredicateInstruction()
2212 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2216 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
2220 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2224 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
2232 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
2240 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL || in PredicateInstruction()
2241 OpC == PPC::BCTRL8 || OpC == PPC::BCTRL_RM || in PredicateInstruction()
2242 OpC == PPC::BCTRL8_RM) { in PredicateInstruction()
2243 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) in PredicateInstruction()
2246 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8 || in PredicateInstruction()
2247 OpC == PPC::BCTRL_RM || OpC == PPC::BCTRL8_RM; in PredicateInstruction()
2250 if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2251 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) in PredicateInstruction()
2252 : (setLR ? PPC::BCCTRL : PPC::BCCTR))); in PredicateInstruction()
2254 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2255 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) in PredicateInstruction()
2256 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn))); in PredicateInstruction()
2259 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) in PredicateInstruction()
2260 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR))); in PredicateInstruction()
2269 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::Implicit) in PredicateInstruction()
2270 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine); in PredicateInstruction()
2271 if (OpC == PPC::BCTRL_RM || OpC == PPC::BCTRL8_RM) in PredicateInstruction()
2273 .addReg(PPC::RM, RegState::ImplicitDefine); in PredicateInstruction()
2283 assert(Pred1.size() == 2 && "Invalid PPC first predicate"); in SubsumesPredicate()
2284 assert(Pred2.size() == 2 && "Invalid PPC second predicate"); in SubsumesPredicate()
2286 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR) in SubsumesPredicate()
2288 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR) in SubsumesPredicate()
2295 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm(); in SubsumesPredicate()
2296 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm(); in SubsumesPredicate()
2302 if (P1 == PPC::PRED_LE && in SubsumesPredicate()
2303 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
2305 if (P1 == PPC::PRED_GE && in SubsumesPredicate()
2306 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
2322 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass, in ClobbersPredicate()
2323 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass }; in ClobbersPredicate()
2354 case PPC::CMPWI: in analyzeCompare()
2355 case PPC::CMPLWI: in analyzeCompare()
2356 case PPC::CMPDI: in analyzeCompare()
2357 case PPC::CMPLDI: in analyzeCompare()
2363 case PPC::CMPW: in analyzeCompare()
2364 case PPC::CMPLW: in analyzeCompare()
2365 case PPC::CMPD: in analyzeCompare()
2366 case PPC::CMPLD: in analyzeCompare()
2367 case PPC::FCMPUS: in analyzeCompare()
2368 case PPC::FCMPUD: in analyzeCompare()
2389 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD) in optimizeCompareInstr()
2402 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW; in optimizeCompareInstr()
2403 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW; in optimizeCompareInstr()
2404 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD; in optimizeCompareInstr()
2444 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
2445 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2446 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2448 if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE) in optimizeCompareInstr()
2450 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
2451 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
2453 if (SubIdx != PPC::sub_eq) in optimizeCompareInstr()
2478 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate; in optimizeCompareInstr()
2507 if (UseMI->getOpcode() != PPC::BCC) in optimizeCompareInstr()
2510 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2511 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2512 unsigned PredHint = PPC::getPredicateHint(Pred); in optimizeCompareInstr()
2517 if (Immed == -1 && PredCond == PPC::PRED_GT) in optimizeCompareInstr()
2520 Pred = PPC::getPredicate(PPC::PRED_GE, PredHint); in optimizeCompareInstr()
2521 else if (Immed == -1 && PredCond == PPC::PRED_LE) in optimizeCompareInstr()
2523 Pred = PPC::getPredicate(PPC::PRED_LT, PredHint); in optimizeCompareInstr()
2524 else if (Immed == 1 && PredCond == PPC::PRED_LT) in optimizeCompareInstr()
2526 Pred = PPC::getPredicate(PPC::PRED_LE, PredHint); in optimizeCompareInstr()
2527 else if (Immed == 1 && PredCond == PPC::PRED_GE) in optimizeCompareInstr()
2529 Pred = PPC::getPredicate(PPC::PRED_GT, PredHint); in optimizeCompareInstr()
2551 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) || in optimizeCompareInstr()
2552 Instr.readsRegister(PPC::CR0, TRI))) in optimizeCompareInstr()
2561 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW || in optimizeCompareInstr()
2562 OpC == PPC::CMPD || OpC == PPC::CMPLD) && in optimizeCompareInstr()
2563 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) && in optimizeCompareInstr()
2586 if (MIOpC == PPC::ANDI_rec || MIOpC == PPC::ANDI8_rec || in optimizeCompareInstr()
2587 MIOpC == PPC::ANDIS_rec || MIOpC == PPC::ANDIS8_rec) in optimizeCompareInstr()
2590 NewOpC = PPC::getRecordFormOpcode(MIOpC); in optimizeCompareInstr()
2591 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1) in optimizeCompareInstr()
2608 if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) && in optimizeCompareInstr()
2633 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
2634 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2635 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2637 PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && in optimizeCompareInstr()
2641 PPC::getSwappedPredicate(Pred))); in optimizeCompareInstr()
2642 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
2643 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
2645 assert((!equalityOnly || NewSubReg == PPC::sub_eq) && in optimizeCompareInstr()
2648 if (NewSubReg == PPC::sub_lt) in optimizeCompareInstr()
2649 NewSubReg = PPC::sub_gt; in optimizeCompareInstr()
2650 else if (NewSubReg == PPC::sub_gt) in optimizeCompareInstr()
2651 NewSubReg = PPC::sub_lt; in optimizeCompareInstr()
2670 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); in optimizeCompareInstr()
2674 MI->clearRegisterDeads(PPC::CR0); in optimizeCompareInstr()
2686 if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) { in optimizeCompareInstr()
2701 NewOpC = MIOpC == PPC::RLWINM in optimizeCompareInstr()
2702 ? (MBInLoHWord ? PPC::ANDI_rec : PPC::ANDIS_rec) in optimizeCompareInstr()
2703 : (MBInLoHWord ? PPC::ANDI8_rec : PPC::ANDIS8_rec); in optimizeCompareInstr()
2711 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec; in optimizeCompareInstr()
2720 } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) { in optimizeCompareInstr()
2724 NewOpC = PPC::ANDI8_rec; in optimizeCompareInstr()
2747 assert(MI->definesRegister(PPC::CR0, /*TRI=*/nullptr) && in optimizeCompareInstr()
2781 if (Opc == PPC::CMPLWI || Opc == PPC::CMPLDI) in optimizeCmpPostRA()
2788 if (Subtarget.isPPC64() && Opc == PPC::CMPWI) in optimizeCmpPostRA()
2802 if (CRReg != PPC::CR0) in optimizeCmpPostRA()
2814 int NewOpC = PPC::getRecordFormOpcode(SrcMIOpc); in optimizeCmpPostRA()
2827 assert(SrcMI->definesRegister(PPC::CR0, /*TRI=*/nullptr) && in optimizeCmpPostRA()
2874 case PPC::STD: in isClusterableLdStOpcPair()
2875 case PPC::STFD: in isClusterableLdStOpcPair()
2876 case PPC::STXSD: in isClusterableLdStOpcPair()
2877 case PPC::DFSTOREf64: in isClusterableLdStOpcPair()
2882 case PPC::STW: in isClusterableLdStOpcPair()
2883 case PPC::STW8: in isClusterableLdStOpcPair()
2884 return SecondOpc == PPC::STW || SecondOpc == PPC::STW8; in isClusterableLdStOpcPair()
2951 if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) { in getInstSizeInBytes()
2968 // PPC always uses a direct mask. in decomposeMachineOperandsTargetFlags()
2976 {MO_PLT, "ppc-plt"}, in getSerializableDirectMachineOperandTargetFlags()
2977 {MO_PIC_FLAG, "ppc-pic"}, in getSerializableDirectMachineOperandTargetFlags()
2978 {MO_PCREL_FLAG, "ppc-pcrel"}, in getSerializableDirectMachineOperandTargetFlags()
2979 {MO_GOT_FLAG, "ppc-got"}, in getSerializableDirectMachineOperandTargetFlags()
2980 {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"}, in getSerializableDirectMachineOperandTargetFlags()
2981 {MO_TLSGD_FLAG, "ppc-tlsgd"}, in getSerializableDirectMachineOperandTargetFlags()
2982 {MO_TPREL_FLAG, "ppc-tprel"}, in getSerializableDirectMachineOperandTargetFlags()
2983 {MO_TLSLDM_FLAG, "ppc-tlsldm"}, in getSerializableDirectMachineOperandTargetFlags()
2984 {MO_TLSLD_FLAG, "ppc-tlsld"}, in getSerializableDirectMachineOperandTargetFlags()
2985 {MO_TLSGDM_FLAG, "ppc-tlsgdm"}, in getSerializableDirectMachineOperandTargetFlags()
2986 {MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"}, in getSerializableDirectMachineOperandTargetFlags()
2987 {MO_GOT_TLSLD_PCREL_FLAG, "ppc-got-tlsld-pcrel"}, in getSerializableDirectMachineOperandTargetFlags()
2988 {MO_GOT_TPREL_PCREL_FLAG, "ppc-got-tprel-pcrel"}, in getSerializableDirectMachineOperandTargetFlags()
2989 {MO_LO, "ppc-lo"}, in getSerializableDirectMachineOperandTargetFlags()
2990 {MO_HA, "ppc-ha"}, in getSerializableDirectMachineOperandTargetFlags()
2991 {MO_TPREL_LO, "ppc-tprel-lo"}, in getSerializableDirectMachineOperandTargetFlags()
2992 {MO_TPREL_HA, "ppc-tprel-ha"}, in getSerializableDirectMachineOperandTargetFlags()
2993 {MO_DTPREL_LO, "ppc-dtprel-lo"}, in getSerializableDirectMachineOperandTargetFlags()
2994 {MO_TLSLD_LO, "ppc-tlsld-lo"}, in getSerializableDirectMachineOperandTargetFlags()
2995 {MO_TOC_LO, "ppc-toc-lo"}, in getSerializableDirectMachineOperandTargetFlags()
2996 {MO_TLS, "ppc-tls"}, in getSerializableDirectMachineOperandTargetFlags()
2997 {MO_PIC_HA_FLAG, "ppc-ha-pic"}, in getSerializableDirectMachineOperandTargetFlags()
2998 {MO_PIC_LO_FLAG, "ppc-lo-pic"}, in getSerializableDirectMachineOperandTargetFlags()
2999 {MO_TPREL_PCREL_FLAG, "ppc-tprel-pcrel"}, in getSerializableDirectMachineOperandTargetFlags()
3000 {MO_TLS_PCREL_FLAG, "ppc-tls-pcrel"}, in getSerializableDirectMachineOperandTargetFlags()
3001 {MO_GOT_PCREL_FLAG, "ppc-got-pcrel"}, in getSerializableDirectMachineOperandTargetFlags()
3015 case PPC::DFLOADf32: in expandVSXMemPseudo()
3016 UpperOpcode = PPC::LXSSP; in expandVSXMemPseudo()
3017 LowerOpcode = PPC::LFS; in expandVSXMemPseudo()
3019 case PPC::DFLOADf64: in expandVSXMemPseudo()
3020 UpperOpcode = PPC::LXSD; in expandVSXMemPseudo()
3021 LowerOpcode = PPC::LFD; in expandVSXMemPseudo()
3023 case PPC::DFSTOREf32: in expandVSXMemPseudo()
3024 UpperOpcode = PPC::STXSSP; in expandVSXMemPseudo()
3025 LowerOpcode = PPC::STFS; in expandVSXMemPseudo()
3027 case PPC::DFSTOREf64: in expandVSXMemPseudo()
3028 UpperOpcode = PPC::STXSD; in expandVSXMemPseudo()
3029 LowerOpcode = PPC::STFD; in expandVSXMemPseudo()
3031 case PPC::XFLOADf32: in expandVSXMemPseudo()
3032 UpperOpcode = PPC::LXSSPX; in expandVSXMemPseudo()
3033 LowerOpcode = PPC::LFSX; in expandVSXMemPseudo()
3035 case PPC::XFLOADf64: in expandVSXMemPseudo()
3036 UpperOpcode = PPC::LXSDX; in expandVSXMemPseudo()
3037 LowerOpcode = PPC::LFDX; in expandVSXMemPseudo()
3039 case PPC::XFSTOREf32: in expandVSXMemPseudo()
3040 UpperOpcode = PPC::STXSSPX; in expandVSXMemPseudo()
3041 LowerOpcode = PPC::STFSX; in expandVSXMemPseudo()
3043 case PPC::XFSTOREf64: in expandVSXMemPseudo()
3044 UpperOpcode = PPC::STXSDX; in expandVSXMemPseudo()
3045 LowerOpcode = PPC::STFDX; in expandVSXMemPseudo()
3047 case PPC::LIWAX: in expandVSXMemPseudo()
3048 UpperOpcode = PPC::LXSIWAX; in expandVSXMemPseudo()
3049 LowerOpcode = PPC::LFIWAX; in expandVSXMemPseudo()
3051 case PPC::LIWZX: in expandVSXMemPseudo()
3052 UpperOpcode = PPC::LXSIWZX; in expandVSXMemPseudo()
3053 LowerOpcode = PPC::LFIWZX; in expandVSXMemPseudo()
3055 case PPC::STIWX: in expandVSXMemPseudo()
3056 UpperOpcode = PPC::STXSIWX; in expandVSXMemPseudo()
3057 LowerOpcode = PPC::STFIWX; in expandVSXMemPseudo()
3065 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
3066 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
3083 case PPC::BUILD_UACC: { in expandPostRAPseudo()
3086 if (ACC - PPC::ACC0 != UACC - PPC::UACC0) { in expandPostRAPseudo()
3087 MCRegister SrcVSR = PPC::VSL0 + (UACC - PPC::UACC0) * 4; in expandPostRAPseudo()
3088 MCRegister DstVSR = PPC::VSL0 + (ACC - PPC::ACC0) * 4; in expandPostRAPseudo()
3093 BuildMI(MBB, MI, DL, get(PPC::XXLOR), DstVSR + VecNo) in expandPostRAPseudo()
3102 case PPC::KILL_PAIR: { in expandPostRAPseudo()
3103 MI.setDesc(get(PPC::UNENCODED_NOP)); in expandPostRAPseudo()
3112 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; in expandPostRAPseudo()
3113 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); in expandPostRAPseudo()
3119 case PPC::PPCLdFixedAddr: { in expandPostRAPseudo()
3123 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; in expandPostRAPseudo()
3124 MI.setDesc(get(PPC::LWZ)); in expandPostRAPseudo()
3159 case PPC::DFLOADf32: in expandPostRAPseudo()
3160 case PPC::DFLOADf64: in expandPostRAPseudo()
3161 case PPC::DFSTOREf32: in expandPostRAPseudo()
3162 case PPC::DFSTOREf64: { in expandPostRAPseudo()
3170 case PPC::XFLOADf32: in expandPostRAPseudo()
3171 case PPC::XFSTOREf32: in expandPostRAPseudo()
3172 case PPC::LIWAX: in expandPostRAPseudo()
3173 case PPC::LIWZX: in expandPostRAPseudo()
3174 case PPC::STIWX: { in expandPostRAPseudo()
3181 case PPC::XFLOADf64: in expandPostRAPseudo()
3182 case PPC::XFSTOREf64: { in expandPostRAPseudo()
3189 case PPC::SPILLTOVSR_LD: { in expandPostRAPseudo()
3191 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
3192 MI.setDesc(get(PPC::DFLOADf64)); in expandPostRAPseudo()
3196 MI.setDesc(get(PPC::LD)); in expandPostRAPseudo()
3199 case PPC::SPILLTOVSR_ST: { in expandPostRAPseudo()
3201 if (PPC::VSFRCRegClass.contains(SrcReg)) { in expandPostRAPseudo()
3203 MI.setDesc(get(PPC::DFSTOREf64)); in expandPostRAPseudo()
3207 MI.setDesc(get(PPC::STD)); in expandPostRAPseudo()
3211 case PPC::SPILLTOVSR_LDX: { in expandPostRAPseudo()
3213 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
3214 MI.setDesc(get(PPC::LXSDX)); in expandPostRAPseudo()
3216 MI.setDesc(get(PPC::LDX)); in expandPostRAPseudo()
3219 case PPC::SPILLTOVSR_STX: { in expandPostRAPseudo()
3221 if (PPC::VSFRCRegClass.contains(SrcReg)) { in expandPostRAPseudo()
3223 MI.setDesc(get(PPC::STXSDX)); in expandPostRAPseudo()
3226 MI.setDesc(get(PPC::STDX)); in expandPostRAPseudo()
3232 case PPC::CFENCE: in expandPostRAPseudo()
3233 case PPC::CFENCE8: { in expandPostRAPseudo()
3235 unsigned CmpOp = Subtarget.isPPC64() ? PPC::CMPD : PPC::CMPW; in expandPostRAPseudo()
3236 BuildMI(MBB, MI, DL, get(CmpOp), PPC::CR7).addReg(Val).addReg(Val); in expandPostRAPseudo()
3237 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP)) in expandPostRAPseudo()
3238 .addImm(PPC::PRED_NE_MINUS) in expandPostRAPseudo()
3239 .addReg(PPC::CR7) in expandPostRAPseudo()
3241 MI.setDesc(get(PPC::ISYNC)); in expandPostRAPseudo()
3257 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) { in selectReg()
3260 case PPC::sub_lt: in selectReg()
3262 case PPC::sub_gt: in selectReg()
3264 case PPC::sub_eq: in selectReg()
3269 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) { in selectReg()
3272 case PPC::sub_lt: in selectReg()
3274 case PPC::sub_gt: in selectReg()
3276 case PPC::sub_eq: in selectReg()
3280 return PPC::NoRegister; in selectReg()
3323 MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec)); in replaceInstrWithLI()
3326 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
3330 MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI)); in replaceInstrWithLI()
3365 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LI8 : PPC::LI), Reg).addImm(Imm); in materializeImmPostRA()
3367 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LIS8 : PPC::LIS), Reg) in materializeImmPostRA()
3370 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::ORI8 : PPC::ORI), Reg) in materializeImmPostRA()
3376 BuildMI(MBB, MBBI, DL, get(PPC::LIS8), Reg).addImm(Imm >> 48); in materializeImmPostRA()
3378 BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg) in materializeImmPostRA()
3381 BuildMI(MBB, MBBI, DL, get(PPC::RLDICR), Reg) in materializeImmPostRA()
3385 BuildMI(MBB, MBBI, DL, get(PPC::ORIS8), Reg) in materializeImmPostRA()
3389 BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg) in materializeImmPostRA()
3416 if (DefMIForTrueReg->getOpcode() == PPC::LI || in getForwardingDefMI()
3417 DefMIForTrueReg->getOpcode() == PPC::LI8 || in getForwardingDefMI()
3418 DefMIForTrueReg->getOpcode() == PPC::ADDI || in getForwardingDefMI()
3419 DefMIForTrueReg->getOpcode() == PPC::ADDI8) { in getForwardingDefMI()
3426 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) in getForwardingDefMI()
3438 Opc == PPC::CMPWI || Opc == PPC::CMPLWI || Opc == PPC::CMPDI || in getForwardingDefMI()
3439 Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 || in getForwardingDefMI()
3440 Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI || in getForwardingDefMI()
3441 Opc == PPC::XORI8 || Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec || in getForwardingDefMI()
3442 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 || in getForwardingDefMI()
3443 Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 || in getForwardingDefMI()
3444 Opc == PPC::RLWINM8_rec; in getForwardingDefMI()
3446 ? PPC::isVFRegister(MI.getOperand(0).getReg()) in getForwardingDefMI()
3452 if ((Opc == PPC::OR || Opc == PPC::OR8) && in getForwardingDefMI()
3469 case PPC::LI: in getForwardingDefMI()
3470 case PPC::LI8: in getForwardingDefMI()
3471 case PPC::ADDItocL8: in getForwardingDefMI()
3472 case PPC::ADDI: in getForwardingDefMI()
3473 case PPC::ADDI8: in getForwardingDefMI()
3585 (ScaleReg == PPC::R0 || ScaleReg == PPC::X0)) in foldFrameOffset()
3628 if (Opc != PPC::ADDI && Opc != PPC::ADDI8) in isADDIInstrEligibleForFolding()
3644 return Opc == PPC::ADD4 || Opc == PPC::ADD8; in isADDInstrEligibleForFolding()
3661 if (XFormOpcode == PPC::INSTRUCTION_LIST_END) in isImmInstrEligibleForFolding()
3666 PPC::isVFRegister(MI.getOperand(0).getReg()), III, true)) in isImmInstrEligibleForFolding()
3766 PPC::INSTRUCTION_LIST_END && in convertToImmediateForm()
3772 ? PPC::isVFRegister(MI.getOperand(0).getReg()) in convertToImmediateForm()
3804 if (SrcMI->getOpcode() != PPC::RLWINM && in combineRLWINM()
3805 SrcMI->getOpcode() != PPC::RLWINM_rec && in combineRLWINM()
3806 SrcMI->getOpcode() != PPC::RLWINM8 && in combineRLWINM()
3807 SrcMI->getOpcode() != PPC::RLWINM8_rec) in combineRLWINM()
3812 "Invalid PPC::RLWINM Instruction!"); in combineRLWINM()
3821 "Invalid PPC::RLWINM Instruction!"); in combineRLWINM()
3864 (MI.getOpcode() == PPC::RLWINM8 || MI.getOpcode() == PPC::RLWINM8_rec); in combineRLWINM()
3869 if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) { in combineRLWINM()
3875 MI.setDesc(get(Is64Bit ? PPC::LI8 : PPC::LI)); in combineRLWINM()
3881 MI.setDesc(get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec)); in combineRLWINM()
3948 case PPC::ADD4: in instrHasImmForm()
3949 case PPC::ADD8: in instrHasImmForm()
3955 III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8; in instrHasImmForm()
3957 case PPC::ADDC: in instrHasImmForm()
3958 case PPC::ADDC8: in instrHasImmForm()
3964 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8; in instrHasImmForm()
3966 case PPC::ADDC_rec: in instrHasImmForm()
3972 III.ImmOpcode = PPC::ADDIC_rec; in instrHasImmForm()
3974 case PPC::SUBFC: in instrHasImmForm()
3975 case PPC::SUBFC8: in instrHasImmForm()
3980 III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8; in instrHasImmForm()
3982 case PPC::CMPW: in instrHasImmForm()
3983 case PPC::CMPD: in instrHasImmForm()
3988 III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI; in instrHasImmForm()
3990 case PPC::CMPLW: in instrHasImmForm()
3991 case PPC::CMPLD: in instrHasImmForm()
3996 III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI; in instrHasImmForm()
3998 case PPC::AND_rec: in instrHasImmForm()
3999 case PPC::AND8_rec: in instrHasImmForm()
4000 case PPC::OR: in instrHasImmForm()
4001 case PPC::OR8: in instrHasImmForm()
4002 case PPC::XOR: in instrHasImmForm()
4003 case PPC::XOR8: in instrHasImmForm()
4010 case PPC::AND_rec: in instrHasImmForm()
4011 III.ImmOpcode = PPC::ANDI_rec; in instrHasImmForm()
4013 case PPC::AND8_rec: in instrHasImmForm()
4014 III.ImmOpcode = PPC::ANDI8_rec; in instrHasImmForm()
4016 case PPC::OR: III.ImmOpcode = PPC::ORI; break; in instrHasImmForm()
4017 case PPC::OR8: III.ImmOpcode = PPC::ORI8; break; in instrHasImmForm()
4018 case PPC::XOR: III.ImmOpcode = PPC::XORI; break; in instrHasImmForm()
4019 case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break; in instrHasImmForm()
4022 case PPC::RLWNM: in instrHasImmForm()
4023 case PPC::RLWNM8: in instrHasImmForm()
4024 case PPC::RLWNM_rec: in instrHasImmForm()
4025 case PPC::RLWNM8_rec: in instrHasImmForm()
4026 case PPC::SLW: in instrHasImmForm()
4027 case PPC::SLW8: in instrHasImmForm()
4028 case PPC::SLW_rec: in instrHasImmForm()
4029 case PPC::SLW8_rec: in instrHasImmForm()
4030 case PPC::SRW: in instrHasImmForm()
4031 case PPC::SRW8: in instrHasImmForm()
4032 case PPC::SRW_rec: in instrHasImmForm()
4033 case PPC::SRW8_rec: in instrHasImmForm()
4034 case PPC::SRAW: in instrHasImmForm()
4035 case PPC::SRAW_rec: in instrHasImmForm()
4045 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || Opc == PPC::RLWNM_rec || in instrHasImmForm()
4046 Opc == PPC::RLWNM8_rec) in instrHasImmForm()
4052 case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
4053 case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
4054 case PPC::RLWNM_rec: in instrHasImmForm()
4055 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
4057 case PPC::RLWNM8_rec: in instrHasImmForm()
4058 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
4060 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
4061 case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
4062 case PPC::SLW_rec: in instrHasImmForm()
4063 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
4065 case PPC::SLW8_rec: in instrHasImmForm()
4066 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
4068 case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
4069 case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
4070 case PPC::SRW_rec: in instrHasImmForm()
4071 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
4073 case PPC::SRW8_rec: in instrHasImmForm()
4074 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
4076 case PPC::SRAW: in instrHasImmForm()
4079 III.ImmOpcode = PPC::SRAWI; in instrHasImmForm()
4081 case PPC::SRAW_rec: in instrHasImmForm()
4084 III.ImmOpcode = PPC::SRAWI_rec; in instrHasImmForm()
4088 case PPC::RLDCL: in instrHasImmForm()
4089 case PPC::RLDCL_rec: in instrHasImmForm()
4090 case PPC::RLDCR: in instrHasImmForm()
4091 case PPC::RLDCR_rec: in instrHasImmForm()
4092 case PPC::SLD: in instrHasImmForm()
4093 case PPC::SLD_rec: in instrHasImmForm()
4094 case PPC::SRD: in instrHasImmForm()
4095 case PPC::SRD_rec: in instrHasImmForm()
4096 case PPC::SRAD: in instrHasImmForm()
4097 case PPC::SRAD_rec: in instrHasImmForm()
4107 if (Opc == PPC::RLDCL || Opc == PPC::RLDCL_rec || Opc == PPC::RLDCR || in instrHasImmForm()
4108 Opc == PPC::RLDCR_rec) in instrHasImmForm()
4114 case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
4115 case PPC::RLDCL_rec: in instrHasImmForm()
4116 III.ImmOpcode = PPC::RLDICL_rec; in instrHasImmForm()
4118 case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break; in instrHasImmForm()
4119 case PPC::RLDCR_rec: in instrHasImmForm()
4120 III.ImmOpcode = PPC::RLDICR_rec; in instrHasImmForm()
4122 case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break; in instrHasImmForm()
4123 case PPC::SLD_rec: in instrHasImmForm()
4124 III.ImmOpcode = PPC::RLDICR_rec; in instrHasImmForm()
4126 case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
4127 case PPC::SRD_rec: in instrHasImmForm()
4128 III.ImmOpcode = PPC::RLDICL_rec; in instrHasImmForm()
4130 case PPC::SRAD: in instrHasImmForm()
4133 III.ImmOpcode = PPC::SRADI; in instrHasImmForm()
4135 case PPC::SRAD_rec: in instrHasImmForm()
4138 III.ImmOpcode = PPC::SRADI_rec; in instrHasImmForm()
4143 case PPC::LBZX: in instrHasImmForm()
4144 case PPC::LBZX8: in instrHasImmForm()
4145 case PPC::LHZX: in instrHasImmForm()
4146 case PPC::LHZX8: in instrHasImmForm()
4147 case PPC::LHAX: in instrHasImmForm()
4148 case PPC::LHAX8: in instrHasImmForm()
4149 case PPC::LWZX: in instrHasImmForm()
4150 case PPC::LWZX8: in instrHasImmForm()
4151 case PPC::LWAX: in instrHasImmForm()
4152 case PPC::LDX: in instrHasImmForm()
4153 case PPC::LFSX: in instrHasImmForm()
4154 case PPC::LFDX: in instrHasImmForm()
4155 case PPC::STBX: in instrHasImmForm()
4156 case PPC::STBX8: in instrHasImmForm()
4157 case PPC::STHX: in instrHasImmForm()
4158 case PPC::STHX8: in instrHasImmForm()
4159 case PPC::STWX: in instrHasImmForm()
4160 case PPC::STWX8: in instrHasImmForm()
4161 case PPC::STDX: in instrHasImmForm()
4162 case PPC::STFSX: in instrHasImmForm()
4163 case PPC::STFDX: in instrHasImmForm()
4173 case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break; in instrHasImmForm()
4174 case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break; in instrHasImmForm()
4175 case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break; in instrHasImmForm()
4176 case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break; in instrHasImmForm()
4177 case PPC::LHAX: III.ImmOpcode = PPC::LHA; break; in instrHasImmForm()
4178 case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break; in instrHasImmForm()
4179 case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break; in instrHasImmForm()
4180 case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break; in instrHasImmForm()
4181 case PPC::LWAX: in instrHasImmForm()
4182 III.ImmOpcode = PPC::LWA; in instrHasImmForm()
4185 case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break; in instrHasImmForm()
4186 case PPC::LFSX: III.ImmOpcode = PPC::LFS; break; in instrHasImmForm()
4187 case PPC::LFDX: III.ImmOpcode = PPC::LFD; break; in instrHasImmForm()
4188 case PPC::STBX: III.ImmOpcode = PPC::STB; break; in instrHasImmForm()
4189 case PPC::STBX8: III.ImmOpcode = PPC::STB8; break; in instrHasImmForm()
4190 case PPC::STHX: III.ImmOpcode = PPC::STH; break; in instrHasImmForm()
4191 case PPC::STHX8: III.ImmOpcode = PPC::STH8; break; in instrHasImmForm()
4192 case PPC::STWX: III.ImmOpcode = PPC::STW; break; in instrHasImmForm()
4193 case PPC::STWX8: III.ImmOpcode = PPC::STW8; break; in instrHasImmForm()
4194 case PPC::STDX: in instrHasImmForm()
4195 III.ImmOpcode = PPC::STD; in instrHasImmForm()
4198 case PPC::STFSX: III.ImmOpcode = PPC::STFS; break; in instrHasImmForm()
4199 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break; in instrHasImmForm()
4202 case PPC::LBZUX: in instrHasImmForm()
4203 case PPC::LBZUX8: in instrHasImmForm()
4204 case PPC::LHZUX: in instrHasImmForm()
4205 case PPC::LHZUX8: in instrHasImmForm()
4206 case PPC::LHAUX: in instrHasImmForm()
4207 case PPC::LHAUX8: in instrHasImmForm()
4208 case PPC::LWZUX: in instrHasImmForm()
4209 case PPC::LWZUX8: in instrHasImmForm()
4210 case PPC::LDUX: in instrHasImmForm()
4211 case PPC::LFSUX: in instrHasImmForm()
4212 case PPC::LFDUX: in instrHasImmForm()
4213 case PPC::STBUX: in instrHasImmForm()
4214 case PPC::STBUX8: in instrHasImmForm()
4215 case PPC::STHUX: in instrHasImmForm()
4216 case PPC::STHUX8: in instrHasImmForm()
4217 case PPC::STWUX: in instrHasImmForm()
4218 case PPC::STWUX8: in instrHasImmForm()
4219 case PPC::STDUX: in instrHasImmForm()
4220 case PPC::STFSUX: in instrHasImmForm()
4221 case PPC::STFDUX: in instrHasImmForm()
4231 case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break; in instrHasImmForm()
4232 case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break; in instrHasImmForm()
4233 case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break; in instrHasImmForm()
4234 case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break; in instrHasImmForm()
4235 case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break; in instrHasImmForm()
4236 case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break; in instrHasImmForm()
4237 case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break; in instrHasImmForm()
4238 case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break; in instrHasImmForm()
4239 case PPC::LDUX: in instrHasImmForm()
4240 III.ImmOpcode = PPC::LDU; in instrHasImmForm()
4243 case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break; in instrHasImmForm()
4244 case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break; in instrHasImmForm()
4245 case PPC::STBUX: III.ImmOpcode = PPC::STBU; break; in instrHasImmForm()
4246 case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break; in instrHasImmForm()
4247 case PPC::STHUX: III.ImmOpcode = PPC::STHU; break; in instrHasImmForm()
4248 case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break; in instrHasImmForm()
4249 case PPC::STWUX: III.ImmOpcode = PPC::STWU; break; in instrHasImmForm()
4250 case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break; in instrHasImmForm()
4251 case PPC::STDUX: in instrHasImmForm()
4252 III.ImmOpcode = PPC::STDU; in instrHasImmForm()
4255 case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break; in instrHasImmForm()
4256 case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break; in instrHasImmForm()
4263 case PPC::LXVX: in instrHasImmForm()
4264 case PPC::LXSSPX: in instrHasImmForm()
4265 case PPC::LXSDX: in instrHasImmForm()
4266 case PPC::STXVX: in instrHasImmForm()
4267 case PPC::STXSSPX: in instrHasImmForm()
4268 case PPC::STXSDX: in instrHasImmForm()
4269 case PPC::XFLOADf32: in instrHasImmForm()
4270 case PPC::XFLOADf64: in instrHasImmForm()
4271 case PPC::XFSTOREf32: in instrHasImmForm()
4272 case PPC::XFSTOREf64: in instrHasImmForm()
4285 case PPC::LXVX: in instrHasImmForm()
4286 III.ImmOpcode = PPC::LXV; in instrHasImmForm()
4289 case PPC::LXSSPX: in instrHasImmForm()
4292 III.ImmOpcode = PPC::LXSSP; in instrHasImmForm()
4294 III.ImmOpcode = PPC::LFS; in instrHasImmForm()
4300 case PPC::XFLOADf32: in instrHasImmForm()
4301 III.ImmOpcode = PPC::DFLOADf32; in instrHasImmForm()
4303 case PPC::LXSDX: in instrHasImmForm()
4306 III.ImmOpcode = PPC::LXSD; in instrHasImmForm()
4308 III.ImmOpcode = PPC::LFD; in instrHasImmForm()
4314 case PPC::XFLOADf64: in instrHasImmForm()
4315 III.ImmOpcode = PPC::DFLOADf64; in instrHasImmForm()
4317 case PPC::STXVX: in instrHasImmForm()
4318 III.ImmOpcode = PPC::STXV; in instrHasImmForm()
4321 case PPC::STXSSPX: in instrHasImmForm()
4324 III.ImmOpcode = PPC::STXSSP; in instrHasImmForm()
4326 III.ImmOpcode = PPC::STFS; in instrHasImmForm()
4332 case PPC::XFSTOREf32: in instrHasImmForm()
4333 III.ImmOpcode = PPC::DFSTOREf32; in instrHasImmForm()
4335 case PPC::STXSDX: in instrHasImmForm()
4338 III.ImmOpcode = PPC::STXSD; in instrHasImmForm()
4340 III.ImmOpcode = PPC::STFD; in instrHasImmForm()
4346 case PPC::XFSTOREf64: in instrHasImmForm()
4347 III.ImmOpcode = PPC::DFSTOREf64; in instrHasImmForm()
4400 // As the algorithm of checking for PPC::ZERO/PPC::ZERO8 in isUseMIElgibleForForwarding()
4421 if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO && in isUseMIElgibleForForwarding()
4422 MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8) in isUseMIElgibleForForwarding()
4439 if (Opc != PPC::ADDItocL8 && Opc != PPC::ADDI && Opc != PPC::ADDI8) in isDefMIElgibleForForwarding()
4445 if (Opc == PPC::ADDItocL8 && Subtarget.isAIX()) in isDefMIElgibleForForwarding()
4510 if (DefMI.getOpcode() == PPC::ADDItocL8) { in isImmElgibleForForwarding()
4559 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) || in simplifyToLI()
4584 case PPC::CMPWI: in simplifyToLI()
4585 case PPC::CMPLWI: in simplifyToLI()
4586 case PPC::CMPDI: in simplifyToLI()
4587 case PPC::CMPLDI: { in simplifyToLI()
4605 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8) in simplifyToLI()
4612 if (RegToCopy == PPC::NoRegister) in simplifyToLI()
4614 // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0. in simplifyToLI()
4615 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) { in simplifyToLI()
4616 CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI)); in simplifyToLI()
4627 CompareUseMI.setDesc(get(PPC::COPY)); in simplifyToLI()
4644 case PPC::ADDI: in simplifyToLI()
4645 case PPC::ADDI8: { in simplifyToLI()
4650 Is64BitLI = Opc == PPC::ADDI8; in simplifyToLI()
4656 case PPC::SUBFIC: in simplifyToLI()
4657 case PPC::SUBFIC8: { in simplifyToLI()
4664 Is64BitLI = Opc == PPC::SUBFIC8; in simplifyToLI()
4670 case PPC::RLDICL: in simplifyToLI()
4671 case PPC::RLDICL_rec: in simplifyToLI()
4672 case PPC::RLDICL_32: in simplifyToLI()
4673 case PPC::RLDICL_32_64: { in simplifyToLI()
4677 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32, in simplifyToLI()
4686 (Opc == PPC::RLDICL_rec && isUInt<16>(InVal.getSExtValue()))) { in simplifyToLI()
4688 Is64BitLI = Opc != PPC::RLDICL_32; in simplifyToLI()
4690 SetCR = Opc == PPC::RLDICL_rec; in simplifyToLI()
4695 case PPC::RLWINM: in simplifyToLI()
4696 case PPC::RLWINM8: in simplifyToLI()
4697 case PPC::RLWINM_rec: in simplifyToLI()
4698 case PPC::RLWINM8_rec: { in simplifyToLI()
4710 ValueFits |= ((Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec) && in simplifyToLI()
4714 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec; in simplifyToLI()
4716 SetCR = Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec; in simplifyToLI()
4721 case PPC::ORI: in simplifyToLI()
4722 case PPC::ORI8: in simplifyToLI()
4723 case PPC::XORI: in simplifyToLI()
4724 case PPC::XORI8: { in simplifyToLI()
4727 if (Opc == PPC::ORI || Opc == PPC::ORI8) in simplifyToLI()
4733 Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8; in simplifyToLI()
4807 assert((XFormOpcode != PPC::INSTRUCTION_LIST_END) && in transformToNewImmFormFedByAdd()
4813 ? PPC::isVFRegister(MI.getOperand(0).getReg()) in transformToNewImmFormFedByAdd()
4924 if (DefMI.getOpcode() == PPC::ADDItocL8) in transformToImmFormFedByAdd()
4962 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) || in transformToImmFormFedByLI()
4998 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) && in transformToImmFormFedByLI()
5001 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) && in transformToImmFormFedByLI()
5007 bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLW_rec || in transformToImmFormFedByLI()
5008 Opc == PPC::SRW || Opc == PPC::SRW_rec || in transformToImmFormFedByLI()
5009 Opc == PPC::SLW8 || Opc == PPC::SLW8_rec || in transformToImmFormFedByLI()
5010 Opc == PPC::SRW8 || Opc == PPC::SRW8_rec; in transformToImmFormFedByLI()
5011 bool SpecialShift64 = Opc == PPC::SLD || Opc == PPC::SLD_rec || in transformToImmFormFedByLI()
5012 Opc == PPC::SRD || Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
5013 bool SetCR = Opc == PPC::SLW_rec || Opc == PPC::SRW_rec || in transformToImmFormFedByLI()
5014 Opc == PPC::SLD_rec || Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
5015 bool RightShift = Opc == PPC::SRW || Opc == PPC::SRW_rec || Opc == PPC::SRD || in transformToImmFormFedByLI()
5016 Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
5043 MI.setDesc(get(PPC::COPY)); in transformToImmFormFedByLI()
5092 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmFormFedByLI()
5093 &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass; in transformToImmFormFedByLI()
5110 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass) in updatedRC()
5111 return &PPC::VSRCRegClass; in updatedRC()
5116 return PPC::getRecordFormOpcode(Opcode); in getRecordFormOpcode()
5120 return (Opcode == PPC::LBZU || Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 || in isOpZeroOfSubwordPreincLoad()
5121 Opcode == PPC::LBZUX8 || Opcode == PPC::LHZU || in isOpZeroOfSubwordPreincLoad()
5122 Opcode == PPC::LHZUX || Opcode == PPC::LHZU8 || in isOpZeroOfSubwordPreincLoad()
5123 Opcode == PPC::LHZUX8); in isOpZeroOfSubwordPreincLoad()
5148 if (Opcode == PPC::RLDICL && MI->getOperand(3).getImm() >= 33) in definedBySignExtendingOp()
5154 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in definedBySignExtendingOp()
5155 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec) && in definedBySignExtendingOp()
5162 if (Opcode == PPC::ANDIS_rec || Opcode == PPC::ANDIS8_rec) { in definedBySignExtendingOp()
5190 if ((isOpZeroOfSubwordPreincLoad(Opcode) || Opcode == PPC::LWZU || in definedByZeroExtendingOp()
5191 Opcode == PPC::LWZUX || Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8) && in definedByZeroExtendingOp()
5197 if (Opcode == PPC::LI || Opcode == PPC::LI8 || in definedByZeroExtendingOp()
5198 Opcode == PPC::LIS || Opcode == PPC::LIS8) { in definedByZeroExtendingOp()
5206 if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in definedByZeroExtendingOp()
5207 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec || in definedByZeroExtendingOp()
5208 Opcode == PPC::RLDICL_32_64) && in definedByZeroExtendingOp()
5212 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in definedByZeroExtendingOp()
5217 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in definedByZeroExtendingOp()
5218 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in definedByZeroExtendingOp()
5219 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in definedByZeroExtendingOp()
5234 Register SPReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in isTOCSaveMI()
5269 case PPC::COPY: { in isSignOrZeroExtended()
5296 if (SrcReg != PPC::X3) { in isSignOrZeroExtended()
5313 if (II == MBB->instr_begin() || (--II)->getOpcode() != PPC::ADJCALLSTACKUP) in isSignOrZeroExtended()
5337 case PPC::ORI: in isSignOrZeroExtended()
5338 case PPC::XORI: in isSignOrZeroExtended()
5339 case PPC::ORI8: in isSignOrZeroExtended()
5340 case PPC::XORI8: { in isSignOrZeroExtended()
5351 case PPC::ORIS: in isSignOrZeroExtended()
5352 case PPC::XORIS: in isSignOrZeroExtended()
5353 case PPC::ORIS8: in isSignOrZeroExtended()
5354 case PPC::XORIS8: { in isSignOrZeroExtended()
5367 case PPC::OR: in isSignOrZeroExtended()
5368 case PPC::OR8: in isSignOrZeroExtended()
5369 case PPC::ISEL: in isSignOrZeroExtended()
5370 case PPC::PHI: { in isSignOrZeroExtended()
5377 if (MI->getOpcode() == PPC::PHI) { in isSignOrZeroExtended()
5399 case PPC::AND: in isSignOrZeroExtended()
5400 case PPC::AND8: { in isSignOrZeroExtended()
5419 return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ)); in isBDNZ()
5437 if (LoopCount->getOpcode() == PPC::LI8 || LoopCount->getOpcode() == PPC::LI) in PPCPipelinerLoopInfo()
5456 MF->getSubtarget<PPCSubtarget>().isPPC64() ? PPC::CTR8 : PPC::CTR, in createTripCountGreaterCondition()
5472 if (LoopCount->getOpcode() == PPC::LI8 || in adjustTripCount()
5473 LoopCount->getOpcode() == PPC::LI) { in adjustTripCount()
5516 unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop); in findLoopInstr()