Lines Matching +full:crypto +full:- +full:rst
1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
16 // ** A lane-sensitive instruction relies, implicitly or explicitly, on **
18 // ** VADDFP is not lane-sensitive, because each lane of the result vector **
20 // ** an instruction like VMULESB is lane-sensitive, because "even" and **
21 // ** "odd" lanes are different for big-endian and little-endian numbering. **
24 // ** are lane-sensitive. If so, they must be added to a switch statement **
29 //===----------------------------------------------------------------------===//
58 // These fragments are provided for little-endian, where the inputs must be
125 // These fragments are provided for little-endian, where the inputs must be
185 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1;
189 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
196 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1;
200 /// VSLDOI_swapped* - These fragments are provided for little-endian, where
207 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1;
260 if (ConstantSDNode *C = cast<BuildVectorSDNode>(N)->getConstantSplatNode())
261 return C->isOne();
264 //===----------------------------------------------------------------------===//
267 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
273 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
281 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
290 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
296 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
304 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
312 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
318 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
336 //===----------------------------------------------------------------------===//
339 def HasAltivec : Predicate<"Subtarget->hasAltivec()">;
412 def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
413 "lvebx $RST, $addr", IIC_LdStLoad,
414 [(set v16i8:$RST, (int_ppc_altivec_lvebx ForceXForm:$addr))]>;
415 def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
416 "lvehx $RST, $addr", IIC_LdStLoad,
417 [(set v8i16:$RST, (int_ppc_altivec_lvehx ForceXForm:$addr))]>;
418 def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
419 "lvewx $RST, $addr", IIC_LdStLoad,
420 [(set v4i32:$RST, (int_ppc_altivec_lvewx ForceXForm:$addr))]>;
421 def LVX : XForm_1_memOp<31, 103, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
422 "lvx $RST, $addr", IIC_LdStLoad,
423 [(set v4i32:$RST, (int_ppc_altivec_lvx ForceXForm:$addr))]>;
424 def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
425 "lvxl $RST, $addr", IIC_LdStLoad,
426 [(set v4i32:$RST, (int_ppc_altivec_lvxl ForceXForm:$addr))]>;
429 def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
430 "lvsl $RST, $addr", IIC_LdStLoad,
431 [(set v16i8:$RST, (int_ppc_altivec_lvsl ForceXForm:$addr))]>,
433 def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
434 "lvsr $RST, $addr", IIC_LdStLoad,
435 [(set v16i8:$RST, (int_ppc_altivec_lvsr ForceXForm:$addr))]>,
439 def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),
440 "stvebx $RST, $addr", IIC_LdStStore,
441 [(int_ppc_altivec_stvebx v16i8:$RST, ForceXForm:$addr)]>;
442 def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),
443 "stvehx $RST, $addr", IIC_LdStStore,
444 [(int_ppc_altivec_stvehx v8i16:$RST, ForceXForm:$addr)]>;
445 def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),
446 "stvewx $RST, $addr", IIC_LdStStore,
447 [(int_ppc_altivec_stvewx v4i32:$RST, ForceXForm:$addr)]>;
448 def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),
449 "stvx $RST, $addr", IIC_LdStStore,
450 [(int_ppc_altivec_stvx v4i32:$RST, ForceXForm:$addr)]>;
451 def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),
452 "stvxl $RST, $addr", IIC_LdStStore,
453 [(int_ppc_altivec_stvxl v4i32:$RST, ForceXForm:$addr)]>;
457 // VA-Form instructions. 3-input AltiVec ops.
487 // VX-Form instructions. AltiVec arithmetic ops.
538 // Defines with the UIM field set to 0 for floating-point
540 // to floating-point (sint_to_fp/uint_to_fp) conversions.
846 let IMM=-1 in {
848 "vspltisw $VD, -1", IIC_VecFP,
851 "vspltisw $VD, -1", IIC_VecFP,
854 "vspltisw $VD, -1", IIC_VecFP,
860 //===----------------------------------------------------------------------===//
999 // These fragments are matched for little-endian, where the inputs must
1023 // are matched for little-endian, where the inputs must be
1124 // Floating-point rounding
1189 def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">;
1190 def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">;
1228 // are matched for little-endian, where the inputs must be swapped for correct
1327 // more fine-grained control than option 1. This would be beneficial
1350 // The cryptography instructions that do not require Category:Vector.Crypto
1398 // Crypto instructions (from builtins)
1416 def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">;
1419 // Vector Multiply-Sum
1441 // VX-Form: [PO VRT / UIM VRB XO].
1458 // Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
1552 // Vector (Bit) Permute (Right-indexed)
1562 // Vector Rotate Left Mask/Mask-Insert
1590 // Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
1596 // Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword
1619 // Decimal Convert From/to National/Zoned/Signed-QWord
1627 // Decimal Copy-Sign/Set-Sign
1633 // Decimal Shift/Unsigned-Shift/Shift-and-Round