Lines Matching full:dispatch

36   // SU is a load; for any predecessors in this dispatch group, that are stores,  in isLoadAfterStore()
62   // SU is a branch; for any predecessors in this dispatch group, with which we  in isBCTRAfterSet()
181       LLVM_DEBUG(dbgs() << "**** Adding to dispatch group: ");  in EmitInstruction()
239 // This models the dispatch group formation of the PPC970 processor.  Dispatch
241 // of instructions.  The PPC970 can dispatch a peak of 4 non-branch and one
244 // There are a number of restrictions to dispatch group formation: some
245 // instructions can only be issued in the first slot of a dispatch group, & some
246 // instructions fill an entire dispatch group.  Additionally, only branches can
252 // branching through it in the same dispatch group, and storing to an address,
253 // then loading from the same address within a dispatch group.  To avoid these
268   LLVM_DEBUG(errs() << "=== Start of dispatch group\n");  in EndDispatchGroup()
321 /// terminate the dispatch group.  We turn NoopHazard for any
322 /// instructions that wouldn't terminate the dispatch group that would cause a
341   // crand/mtspr/etc) if this is the first cycle of the dispatch group.  in getHazardType()
347   // already in the dispatch group.  in getHazardType()
369   // Do not allow MTCTR and BCTRL to be in the same dispatch group.  in getHazardType()
426   assert(NumIssued < 5 && "Illegal dispatch group!");  in AdvanceCycle()