246   MachineBasicBlock *Exiting = Dec->getParent();  in expandNormalLoops()  local
247   assert((Preheader && Exiting) &&  in expandNormalLoops()
248          "Preheader and exiting should exist for CTR loop!");  in expandNormalLoops()
271   // Generate "addi -1" in the exiting block.  in expandNormalLoops()
272   BuildMI(*Exiting, Dec, Dec->getDebugLoc(), TII->get(ADDIOpcode), ADDIDef)  in expandNormalLoops()
277   if (ML->isLoopLatch(Exiting)) {  in expandNormalLoops()
279     // Preheader and the other one is loop latch Exiting. In hardware loop  in expandNormalLoops()
284     PHIMIB.addReg(ADDIDef).addMBB(Exiting);  in expandNormalLoops()
301   // Generate the compare in the exiting block.  in expandNormalLoops()
304       BuildMI(*Exiting, Dec, Dec->getDebugLoc(), TII->get(CMPOpcode), CMPDef)  in expandNormalLoops()
308   BuildMI(*Exiting, Dec, Dec->getDebugLoc(), TII->get(TargetOpcode::COPY),  in expandNormalLoops()
323   MachineBasicBlock *Exiting = Dec->getParent();  in expandCTRLoops()  local
326   assert((Preheader && Exiting) &&  in expandCTRLoops()
327          "Preheader and exiting should exist for CTR loop!");  in expandCTRLoops()
354   // Generate "bdnz/bdz" in the exiting block just before the terminator.  in expandCTRLoops()
355   BuildMI(*Exiting, &*BrInstr, BrInstr->getDebugLoc(), TII->get(Opcode))  in expandCTRLoops()