Lines Matching +full:protect +full:- +full:exec
1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 // Get the target-independent interfaces which we are implementing.
17 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
59 // Specifies that the selected CPU supports 64-bit instructions, regardless of
60 // whether we are in 32-bit or 64-bit mode.
62 "Enable 64-bit instructions">;
65 : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
67 def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
68 "Enable floating-point instructions">;
70 // Specifies that we are in 64-bit mode or that we should use 64-bit registers
71 // in 32-bit mode when possible. Requires Feature64Bit to be enabled.
73 "Enable 64-bit registers usage for ppc32 [beta]">;
78 "Use condition-register bits individually">;
89 "Enable Embedded Floating-Point APU 2 instructions",
123 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
145 def FeatureSecurePlt : SubtargetFeature<"secure-plt","IsSecurePlt", "true",
155 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
156 "Requires two constant Newton-Raphson computation">;
157 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
163 def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
167 SubtargetFeature<"direct-move", "HasDirectMove", "true",
170 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
173 def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics",
177 SubtargetFeature<"invariant-function-descriptors",
188 def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
190 "Power8 Addi-Load fusion",
192 def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
194 "Power8 Addis-Load fusion",
196 def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",
200 SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true",
204 SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true",
208 SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true",
212 SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true",
216 SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true",
220 SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true",
224 SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true",
225 "Target supports Wide-Immediate fusion",
228 SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true",
232 SubtargetFeature<"fuse-back2back", "HasBack2BackFusion", "true",
236 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
239 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
240 "Use PowerPC pre-RA scheduling strategy">;
242 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
243 "Use PowerPC post-RA scheduling strategy">;
246 "Enable the __float128 data type for IEEE-754R Binary128.",
254 def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
261 def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
264 def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
267 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
271 def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
275 def FeatureISAFuture : SubtargetFeature<"isa-future-instructions",
279 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
282 def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
286 def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector",
293 def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
297 def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
302 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
306 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
314 SubtargetFeature<"rop-protect", "HasROPProtect", "true",
315 "Add ROP protect">;
321 // Specifies that local-exec TLS accesses in any function with this target
322 // attribute should use the optimized TOC-free sequence (where the offset is an
323 // immediate off of R13 for which the linker might add fix-up code if the
328 SubtargetFeature<"aix-small-local-exec-tls", "HasAIXSmallLocalExecTLS", "true",
329 "Produce a TOC-free local-exec TLS sequence for this function "
330 "for 64-bit AIX">;
332 // Specifies that local-dynamic TLS accesses in any function with this target
334 // off the module-handle for which the linker might add fix-up code for if the
337 SubtargetFeature<"aix-small-local-dynamic-tls", "HasAIXSmallLocalDynamicTLS",
338 "true", "Produce a faster local-dynamic TLS sequence for this "
339 "function for 64-bit AIX">;
342 SubtargetFeature<"aix-shared-lib-tls-model-opt",
345 "with the main program (for 64-bit AIX only)">;
348 SubtargetFeature<"predictable-select-expensive",
353 def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
445 // this list also includes scheduling-related features since we do not have
497 // DFP p6, p6x, p7 decimal floating-point instructions
500 //===----------------------------------------------------------------------===//
502 //===----------------------------------------------------------------------===//
503 // RecFormRel - Filter class used to relate non-record-form instructions with
504 // their record-form variants.
507 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
508 // FMA instruction forms with their corresponding factor-killing forms.
513 //===----------------------------------------------------------------------===//
515 //===----------------------------------------------------------------------===//
524 // The key column are the non-record-form instructions.
537 // The key column are the record-form instructions.
549 // The key column are the (default) addend-killing instructions.
555 //===----------------------------------------------------------------------===//
557 //===----------------------------------------------------------------------===//
563 //===----------------------------------------------------------------------===//
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706 //===----------------------------------------------------------------------===//
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