Lines Matching +full:per +full:- +full:slice

1 //===- P9InstrResources.td - P9 Instruction Resource Defs  -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 //   - Each CPU is made up of two superslices.
17 //   - Each superslice is made up of two slices. Therefore, there are 4 slices
19 //   - Up to 6 instructions can be dispatched to each CPU. Three per superslice.
20 //   - Each CPU has:
21 //     - One CY (Crypto) unit P9_CY_*
22 //     - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_*
23 //     - Two PM (Permute) units. One on each superslice. P9_PM_*
24 //     - Two DIV (Fixed Point Divide) units. One on each superslize. P9_DIV_*
25 //     - Four ALU (Fixed Point Arithmetic) units. One on each slice. P9_ALU_*
26 //     - Four DP (Floating Point) units. One on each slice. P9_DP_*
28 //     - Four AGEN (Address Generation) units. One for each slice. P9_AGEN_*
29 //     - Four Load/Store Queues. P9_LS_*
30 //   - Each set of instructions will require a number of these resources.
31 //===----------------------------------------------------------------------===//
87 // single slice. However, since it is Restricted, it requires all 3 dispatches
104 // Standard Dispatch ALU operation for 3 cycles. Only one slice used.
121 // Standard Dispatch ALU operation for 2 cycles. Only one slice used.
177 // single slice. However, since it is Restricted, it requires all 3 dispatches
524 // Three Cycle PM operation. Only one PM unit per superslice so we use the whole
634 // 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
658 // 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
666 // 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
683 // 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
691 // 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
700 // 76 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
709 // 6 Cycle Load uses a single slice.
715 // 5 Cycle Load uses a single slice.
734 // 4 Cycle Load uses a single slice.
762 // 4 Cycle Restricted load uses a single slice but the dispatch for the whole
870 // Cracked 3-Way Load Instruction
892 // Single slice Restricted store operation. The restricted operation requires
920 // 5 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
929 // 12 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
943 // 16 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
955 // 24 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
973 // 40 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
984 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
985 // and one full superslice for the DIV operation since there is only one DIV per
993 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
994 // and one full superslice for the DIV operation since there is only one DIV per
1009 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
1010 // and one full superslice for the DIV operation since there is only one DIV per
1130 // 33 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1144 // Instruction can be done on a single slice.
1150 // 36 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1183 // 26 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1196 // 33 Cycle DP Instruction. Takes one slice and 1 dispatch.
1202 // 22 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1215 // 22 Cycle DP Instruction. Takes one slice and 1 dispatch.
1284 // 6 Cycle CY operation. Only one CY unit per CPU so we use a whole