Lines Matching refs:dst4
2296 regclass:$dst4), (ins Int32Regs:$src),
2299 regclass:$dst4), (ins Int64Regs:$src),
2302 regclass:$dst4), (ins MEMri:$src),
2305 regclass:$dst4), (ins MEMri64:$src),
2308 regclass:$dst4), (ins imemAny:$src),
2325 : VLDU_G_ELE_V4<"v4.u8 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int16Regs>;
2327 : VLDU_G_ELE_V4<"v4.u16 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
2330 : VLDU_G_ELE_V4<"v4.u32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
2333 : VLDU_G_ELE_V4<"v4.b16 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
2336 : VLDU_G_ELE_V4<"v4.b32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
2339 : VLDU_G_ELE_V4<"v4.f32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
2405 regclass:$dst4), (ins Int32Regs:$src),
2408 regclass:$dst4), (ins Int64Regs:$src),
2411 regclass:$dst4), (ins MEMri:$src),
2414 regclass:$dst4), (ins MEMri64:$src),
2417 regclass:$dst4), (ins imemAny:$src),
2435 : VLDG_G_ELE_V4<"v4.u8 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int16Regs>;
2437 : VLDG_G_ELE_V4<"v4.u16 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int16Regs>;
2439 : VLDG_G_ELE_V4<"v4.u32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int32Regs>;
2441 : VLDG_G_ELE_V4<"v4.f32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Float32Regs>;