MipsSEFrameLowering.cpp - OpenGrok cross reference for /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp

Lines Matching refs:Mips
50   if (Mips::ACC64RegClass.contains(Src))  in getMFHiLoOpc()
51     return std::make_pair((unsigned)Mips::PseudoMFHI,  in getMFHiLoOpc()
52                           (unsigned)Mips::PseudoMFLO);  in getMFHiLoOpc()
54   if (Mips::ACC64DSPRegClass.contains(Src))  in getMFHiLoOpc()
55     return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);  in getMFHiLoOpc()
57   if (Mips::ACC128RegClass.contains(Src))  in getMFHiLoOpc()
58     return std::make_pair((unsigned)Mips::PseudoMFHI64,  in getMFHiLoOpc()
59                           (unsigned)Mips::PseudoMFLO64);  in getMFHiLoOpc()
117   case Mips::LOAD_CCOND_DSP:  in expandInstr()
120   case Mips::STORE_CCOND_DSP:  in expandInstr()
123   case Mips::LOAD_ACC64:  in expandInstr()
124   case Mips::LOAD_ACC64DSP:  in expandInstr()
127   case Mips::LOAD_ACC128:  in expandInstr()
130   case Mips::STORE_ACC64:  in expandInstr()
131     expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);  in expandInstr()
133   case Mips::STORE_ACC64DSP:  in expandInstr()
134     expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);  in expandInstr()
136   case Mips::STORE_ACC128:  in expandInstr()
137     expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);  in expandInstr()
139   case Mips::BuildPairF64:  in expandInstr()
143   case Mips::BuildPairF64_64:  in expandInstr()
147   case Mips::ExtractElementF64:  in expandInstr()
151   case Mips::ExtractElementF64_64:  in expandInstr()
210   Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);  in expandLoadACC()
211   Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);  in expandLoadACC()
268   Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);  in expandCopyACC()
269   Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);  in expandCopyACC()
306       && I->getOperand(3).getReg() == Mips::SP) {  in expandBuildPairF64()
317     const TargetRegisterClass *RC = &Mips::GPR32RegClass;  in expandBuildPairF64()
319         FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;  in expandBuildPairF64()
350     BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);  in expandExtractElementF64()
371       && I->getOperand(3).getReg() == Mips::SP) {  in expandExtractElementF64()
384         FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;  in expandExtractElementF64()
385     const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;  in expandExtractElementF64()
419   unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;  in emitPrologue()
422         &Mips::GPR64RegClass : &Mips::GPR32RegClass;  in emitPrologue()
460       if (Mips::AFGR64RegClass.contains(Reg)) {  in emitPrologue()
462             MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);  in emitPrologue()
464             MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);  in emitPrologue()
478       } else if (Mips::FGR64RegClass.contains(Reg)) {  in emitPrologue()
550         unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;  in emitPrologue()
590   const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;  in emitInterruptPrologueStub()
596     MBB.addLiveIn(Mips::COP013);  in emitInterruptPrologueStub()
597     BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)  in emitInterruptPrologueStub()
598         .addReg(Mips::COP013)  in emitInterruptPrologueStub()
602     BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)  in emitInterruptPrologueStub()
603         .addReg(Mips::K0)  in emitInterruptPrologueStub()
610   MBB.addLiveIn(Mips::COP014);  in emitInterruptPrologueStub()
611   BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)  in emitInterruptPrologueStub()
612       .addReg(Mips::COP014)  in emitInterruptPrologueStub()
616   STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,  in emitInterruptPrologueStub()
621   MBB.addLiveIn(Mips::COP012);  in emitInterruptPrologueStub()
622   BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)  in emitInterruptPrologueStub()
623       .addReg(Mips::COP012)  in emitInterruptPrologueStub()
627   STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,  in emitInterruptPrologueStub()
635   unsigned SrcReg = Mips::ZERO;  in emitInterruptPrologueStub()
640     SrcReg = Mips::K0;  in emitInterruptPrologueStub()
656   BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)  in emitInterruptPrologueStub()
660       .addReg(Mips::K1)  in emitInterruptPrologueStub()
664   BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)  in emitInterruptPrologueStub()
665       .addReg(Mips::ZERO)  in emitInterruptPrologueStub()
668       .addReg(Mips::K1)  in emitInterruptPrologueStub()
673     BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)  in emitInterruptPrologueStub()
674         .addReg(Mips::ZERO)  in emitInterruptPrologueStub()
677         .addReg(Mips::K1)  in emitInterruptPrologueStub()
681   BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)  in emitInterruptPrologueStub()
682       .addReg(Mips::K1)  in emitInterruptPrologueStub()
719         ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;  in emitEpilogue()
754   const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;  in emitInterruptEpilogueStub()
757   BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);  in emitInterruptEpilogueStub()
758   BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));  in emitInterruptEpilogueStub()
761   STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,  in emitInterruptEpilogueStub()
764   BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)  in emitInterruptEpilogueStub()
765       .addReg(Mips::K1)  in emitInterruptEpilogueStub()
769   STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,  in emitInterruptEpilogueStub()
772   BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)  in emitInterruptEpilogueStub()
773       .addReg(Mips::K1)  in emitInterruptEpilogueStub()
806     bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)  in spillCalleeSavedRegisters()
813     bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 ||  in spillCalleeSavedRegisters()
814                    Reg == Mips::HI0 || Reg == Mips::HI0_64);  in spillCalleeSavedRegisters()
821         Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;  in spillCalleeSavedRegisters()
822         Reg = Mips::K0;  in spillCalleeSavedRegisters()
824         Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64;  in spillCalleeSavedRegisters()
825         Reg = Mips::K0_64;  in spillCalleeSavedRegisters()
827       BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)  in spillCalleeSavedRegisters()
867   unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;  in determineCalleeSaves()
869   unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7;  in determineCalleeSaves()
895       Mips::GPR64RegClass : Mips::GPR32RegClass;  in determineCalleeSaves()
911       ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass;  in determineCalleeSaves()
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