Lines Matching +full:odd +full:- +full:numbered
1 //===- MipsSEFrameLowering.cpp - Mips32/64 Frame Information --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
116 switch(I->getOpcode()) { in expandInstr()
171 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandLoadCCond()
175 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); in expandLoadCCond()
178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
186 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandStoreCCond()
190 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); in expandStoreCCond()
192 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
193 .addReg(Src, getKillRegState(I->getOperand(0).isKill())); in expandStoreCCond()
204 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandLoadACC()
209 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); in expandLoadACC()
212 DebugLoc DL = I->getDebugLoc(); in expandLoadACC()
229 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandStoreACC()
234 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); in expandStoreACC()
235 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill()); in expandStoreACC()
236 DebugLoc DL = I->getDebugLoc(); in expandStoreACC()
245 Register Src = I->getOperand(1).getReg(); in expandCopy()
261 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg(); in expandCopyACC()
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill()); in expandCopyACC()
270 DebugLoc DL = I->getDebugLoc(); in expandCopyACC()
296 // for odd-numbered double precision values (because the lower 32-bits is in expandBuildPairF64()
300 // double-precision values in regardless of being an odd/even register. in expandBuildPairF64()
305 if (I->getNumOperands() == 4 && I->getOperand(3).isReg() in expandBuildPairF64()
306 && I->getOperand(3).getReg() == Mips::SP) { in expandBuildPairF64()
307 Register DstReg = I->getOperand(0).getReg(); in expandBuildPairF64()
308 Register LoReg = I->getOperand(1).getReg(); in expandBuildPairF64()
309 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64()
311 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are in expandBuildPairF64()
312 // the cases where mthc1 is not available). 64-bit architectures and in expandBuildPairF64()
321 // We re-use the same spill slot each time so that the stack frame doesn't in expandBuildPairF64()
323 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(MF, RC2); in expandBuildPairF64()
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
345 const MachineOperand &Op1 = I->getOperand(1); in expandExtractElementF64()
346 const MachineOperand &Op2 = I->getOperand(2); in expandExtractElementF64()
349 Register DstReg = I->getOperand(0).getReg(); in expandExtractElementF64()
350 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg); in expandExtractElementF64()
361 // for odd-numbered double precision values (because the lower 32-bits is in expandExtractElementF64()
365 // double-precision values in regardless of being an odd/even register. in expandExtractElementF64()
370 if (I->getNumOperands() == 4 && I->getOperand(3).isReg() in expandExtractElementF64()
371 && I->getOperand(3).getReg() == Mips::SP) { in expandExtractElementF64()
372 Register DstReg = I->getOperand(0).getReg(); in expandExtractElementF64()
375 int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N)); in expandExtractElementF64()
377 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are in expandExtractElementF64()
378 // the cases where mfhc1 is not available). 64-bit architectures and in expandExtractElementF64()
387 // We re-use the same spill slot each time so that the stack frame doesn't in expandExtractElementF64()
389 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(MF, RC); in expandExtractElementF64()
433 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); in emitPrologue()
447 // Find the instruction past the last instruction that saves a callee-saved in emitPrologue()
452 // Iterate over list of callee-saved registers and emit .cfi_offset in emitPrologue()
462 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); in emitPrologue()
464 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); in emitPrologue()
479 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue()
480 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue()
497 nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); in emitPrologue()
504 if (MipsFI->callsEhReturn()) { in emitPrologue()
510 MipsFI->getEhDataRegFI(I), RC, &RegInfo, in emitPrologue()
516 int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I)); in emitPrologue()
517 unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true); in emitPrologue()
533 nullptr, MRI->getDwarfRegNum(FP, true))); in emitPrologue()
538 // addiu $Reg, $zero, -MaxAlignment in emitPrologue()
543 int64_t MaxAlign = -(int64_t)MFI.getMaxAlign().value(); in emitPrologue()
563 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); in emitInterruptPrologueStub()
572 "\"interrupt\" attribute is not supported on pre-MIPS32R2 or " in emitInterruptPrologueStub()
597 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0) in emitInterruptPrologueStub()
602 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0) in emitInterruptPrologueStub()
611 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1) in emitInterruptPrologueStub()
616 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false, in emitInterruptPrologueStub()
617 MipsFI->getISRRegFI(0), PtrRC, in emitInterruptPrologueStub()
622 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1) in emitInterruptPrologueStub()
627 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false, in emitInterruptPrologueStub()
628 MipsFI->getISRRegFI(1), PtrRC, in emitInterruptPrologueStub()
656 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
664 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
673 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
681 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptPrologueStub()
698 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); in emitEpilogue()
707 // Find the first instruction that restores a callee-saved register. in emitEpilogue()
711 --I; in emitEpilogue()
717 if (MipsFI->callsEhReturn()) { in emitEpilogue()
721 // Find first instruction that restores a callee-saved register. in emitEpilogue()
724 --I; in emitEpilogue()
729 MipsFI->getEhDataRegFI(J), RC, &RegInfo, in emitEpilogue()
751 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); in emitInterruptEpilogueStub()
757 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO); in emitInterruptEpilogueStub()
758 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB)); in emitInterruptEpilogueStub()
761 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1, in emitInterruptEpilogueStub()
762 MipsFI->getISRRegFI(0), PtrRC, in emitInterruptEpilogueStub()
764 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014) in emitInterruptEpilogueStub()
769 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1, in emitInterruptEpilogueStub()
770 MipsFI->getISRRegFI(1), PtrRC, in emitInterruptEpilogueStub()
772 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptEpilogueStub()
788 return StackOffset::getFixed(MFI.getObjectOffset(FI) + MFI.getStackSize() - in getFrameIndexReference()
800 // Add the callee-saved register as live-in. Do not add if the register is in spillCalleeSavedRegisters()
807 && MF->getFrameInfo().isReturnAddressTaken(); in spillCalleeSavedRegisters()
815 const Function &Func = MBB.getParent()->getFunction(); in spillCalleeSavedRegisters()
817 DebugLoc DL = MI->getDebugLoc(); in spillCalleeSavedRegisters()
833 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
844 // Reserve call frame if the size of the maximum call frame fits into 16-bit in hasReservedCallFrame()
881 if (MipsFI->callsEhReturn()) in determineCalleeSaves()
882 MipsFI->createEhDataRegsFI(MF); in determineCalleeSaves()
885 if (MipsFI->isISR()) in determineCalleeSaves()
886 MipsFI->createISRRegFI(MF); in determineCalleeSaves()
892 // general-purpose registers 64 bits wide, it should be 64-bit, otherwise in determineCalleeSaves()
893 // it should be 32-bit. in determineCalleeSaves()
896 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), in determineCalleeSaves()
897 TRI->getSpillAlign(RC), false); in determineCalleeSaves()
898 RS->addScavengingFrameIndex(FI); in determineCalleeSaves()
912 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), in determineCalleeSaves()
913 TRI->getSpillAlign(RC), false); in determineCalleeSaves()
914 RS->addScavengingFrameIndex(FI); in determineCalleeSaves()