Lines Matching full:mips

1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
23 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
44     return Mips::CPU16RegsRegClass;
47     return Mips::GPRMM16RegClass;
50     return Mips::GPR64RegClass;
52   return Mips::GPR32RegClass;
82   RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
88     MF.getRegInfo().addLiveIn(Mips::T9_64);
89     MBB.addLiveIn(Mips::T9_64);
95     BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
97     BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
98         .addReg(Mips::T9_64);
99     BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
109     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
111     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
116   MF.getRegInfo().addLiveIn(Mips::T9);
117   MBB.addLiveIn(Mips::T9);
124     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
126     BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
127     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
148   // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
151   MF.getRegInfo().addLiveIn(Mips::V0);
152   MBB.addLiveIn(Mips::V0);
153   BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
154       .addReg(Mips::V0).addReg(Mips::T9);
162             ? Mips::GPR64RegClass
163             : Mips::GPR32RegClass;
175   const TargetRegisterClass &RC = Mips::GPR32RegClass;