Lines Matching refs:Mips
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
128 return &Mips::GPR32RegClass; in getRegClassForTypeOnBank()
136 return &Mips::FGR32RegClass; in getRegClassForTypeOnBank()
137 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in getRegClassForTypeOnBank()
150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
168 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm()
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm()
171 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg}) in materialize32BitImm()
200 return Mips::SW; in selectLoadStoreOpCode()
202 return Mips::SH; in selectLoadStoreOpCode()
204 return Mips::SB; in selectLoadStoreOpCode()
212 return Mips::LW; in selectLoadStoreOpCode()
214 return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu; in selectLoadStoreOpCode()
216 return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LB : Mips::LBu; in selectLoadStoreOpCode()
229 return isStore ? Mips::SWC1 : Mips::LWC1; in selectLoadStoreOpCode()
232 return isStore ? Mips::SDC164 : Mips::LDC164; in selectLoadStoreOpCode()
233 return isStore ? Mips::SDC1 : Mips::LDC1; in selectLoadStoreOpCode()
242 return isStore ? Mips::ST_B : Mips::LD_B; in selectLoadStoreOpCode()
244 return isStore ? Mips::ST_H : Mips::LD_H; in selectLoadStoreOpCode()
246 return isStore ? Mips::ST_W : Mips::LD_W; in selectLoadStoreOpCode()
248 return isStore ? Mips::ST_D : Mips::LD_D; in selectLoadStoreOpCode()
300 if (I.getOpcode() == Mips::G_MUL && in select()
302 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) in select()
323 Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); in select()
326 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) in select()
333 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) in select()
343 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
355 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
367 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
368 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) in select()
375 Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
376 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
383 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
385 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
395 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
397 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
407 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) in select()
416 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) in select()
466 if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO)) in select()
468 if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO)) in select()
475 Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
476 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) in select()
478 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
479 if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3, in select()
482 if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(), in select()
507 Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); in select()
513 TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV)) in select()
521 TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI)) in select()
532 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)) in select()
550 STI.isFP64bit() ? Mips::ExtractElementF64_64 : Mips::ExtractElementF64; in select()
571 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) in select()
593 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
599 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
604 Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
605 Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
613 STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, in select()
625 Size == 32 ? Mips::FABS_S in select()
626 : STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32; in select()
642 Opcode = Mips::TRUNC_W_S; in select()
644 Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32; in select()
645 Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass); in select()
652 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) in select()
664 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
684 Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
688 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
697 Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
699 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
707 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
720 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
730 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
744 if (Opcode == Mips::SLTiu || Opcode == Mips::XORi) in select()
752 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
760 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS); in select()
761 Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1); in select()
764 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS); in select()
765 Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp); in select()
768 Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS); in select()
771 Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS); in select()
772 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); in select()
775 Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS); in select()
778 Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS); in select()
779 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); in select()
782 Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS); in select()
785 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); in select()
786 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); in select()
789 Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS); in select()
792 Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS); in select()
793 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); in select()
823 MipsFCMPCondCode = Mips::FCOND_UN; in select()
828 MipsFCMPCondCode = Mips::FCOND_OEQ; in select()
833 MipsFCMPCondCode = Mips::FCOND_UEQ; in select()
838 MipsFCMPCondCode = Mips::FCOND_OLT; in select()
843 MipsFCMPCondCode = Mips::FCOND_ULT; in select()
848 MipsFCMPCondCode = Mips::FCOND_OLE; in select()
853 MipsFCMPCondCode = Mips::FCOND_ULE; in select()
864 unsigned MoveOpcode = isLogicallyNegated ? Mips::MOVT_I : Mips::MOVF_I; in select()
866 Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
867 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
869 .addUse(Mips::ZERO) in select()
874 Size == 32 ? Mips::FCMP_S32 in select()
875 : STI.isFP64bit() ? Mips::FCMP_D64 : Mips::FCMP_D32; in select()
885 .addUse(Mips::ZERO) in select()
886 .addUse(Mips::FCC0) in select()
895 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0); in select()
902 Register LeaReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
904 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu)) in select()
911 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW)) in select()