Lines Matching +full:custom +full:- +full:temp
1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
82 #define DEBUG_TYPE "mips-lower"
87 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
142 return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty); in getGlobalReg()
148 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); in getTargetNode()
154 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); in getTargetNode()
160 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); in getTargetNode()
166 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); in getTargetNode()
172 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(), in getTargetNode()
173 N->getOffset(), Flag); in getTargetNode()
305 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA in MipsTargetLowering()
318 // MIPS doesn't have extending float->double load/store. Set LoadExtAction in MipsTargetLowering()
343 // Mips Custom Operations in MipsTargetLowering()
345 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in MipsTargetLowering()
346 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in MipsTargetLowering()
347 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in MipsTargetLowering()
348 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in MipsTargetLowering()
349 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in MipsTargetLowering()
350 setOperationAction(ISD::SELECT, MVT::f32, Custom); in MipsTargetLowering()
351 setOperationAction(ISD::SELECT, MVT::f64, Custom); in MipsTargetLowering()
352 setOperationAction(ISD::SELECT, MVT::i32, Custom); in MipsTargetLowering()
353 setOperationAction(ISD::SETCC, MVT::f32, Custom); in MipsTargetLowering()
354 setOperationAction(ISD::SETCC, MVT::f64, Custom); in MipsTargetLowering()
355 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in MipsTargetLowering()
356 setOperationAction(ISD::FABS, MVT::f32, Custom); in MipsTargetLowering()
357 setOperationAction(ISD::FABS, MVT::f64, Custom); in MipsTargetLowering()
358 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in MipsTargetLowering()
359 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in MipsTargetLowering()
360 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in MipsTargetLowering()
376 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in MipsTargetLowering()
377 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); in MipsTargetLowering()
378 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); in MipsTargetLowering()
379 setOperationAction(ISD::JumpTable, MVT::i64, Custom); in MipsTargetLowering()
380 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); in MipsTargetLowering()
381 setOperationAction(ISD::SELECT, MVT::i64, Custom); in MipsTargetLowering()
386 setOperationAction(ISD::LOAD, MVT::i64, Custom); in MipsTargetLowering()
387 setOperationAction(ISD::STORE, MVT::i64, Custom); in MipsTargetLowering()
389 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in MipsTargetLowering()
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); in MipsTargetLowering()
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); in MipsTargetLowering()
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); in MipsTargetLowering()
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in MipsTargetLowering()
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in MipsTargetLowering()
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in MipsTargetLowering()
401 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); in MipsTargetLowering()
403 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); in MipsTargetLowering()
471 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); in MipsTargetLowering()
473 setOperationAction(ISD::VASTART, MVT::Other, Custom); in MipsTargetLowering()
474 setOperationAction(ISD::VAARG, MVT::Other, Custom); in MipsTargetLowering()
509 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
510 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
511 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
512 setTruncStoreAction(MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
527 // The arguments on the stack are defined in terms of 4-byte slots on O32 in MipsTargetLowering()
528 // and 8-byte slots on N32/N64. in MipsTargetLowering()
553 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); in createFastISel()
582 EVT Ty = N->getValueType(0); in performDivRemCombine()
585 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : in performDivRemCombine()
590 N->getOperand(0), N->getOperand(1)); in performDivRemCombine()
595 if (N->hasAnyUseOfValue(0)) { in performDivRemCombine()
604 if (N->hasAnyUseOfValue(1)) { in performDivRemCombine()
668 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in createFPCmp()
678 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); in createCMovFP()
691 SDValue SetCC = N->getOperand(0); in performSELECTCombine()
697 SDValue False = N->getOperand(2); in performSELECTCombine()
717 if (!FalseC->getZExtValue()) { in performSELECTCombine()
718 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
719 SDValue True = N->getOperand(1); in performSELECTCombine()
730 SDValue True = N->getOperand(1); in performSELECTCombine()
738 // of a SETCC operator is always MVT::i32 for non-vector types. in performSELECTCombine()
742 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); in performSELECTCombine()
744 // 1) (a < x) ? y : y-1 in performSELECTCombine()
746 // addiu $reg2, $reg1, y-1 in performSELECTCombine()
750 // 2) (a < x) ? y-1 : y in performSELECTCombine()
753 // addiu $reg2, $reg1, y-1 in performSELECTCombine()
754 if (Diff == -1) { in performSELECTCombine()
755 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
772 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); in performCMovFPCombine()
775 if (!FalseC || FalseC->getZExtValue()) in performCMovFPCombine()
785 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : in performCMovFPCombine()
788 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); in performCMovFPCombine()
799 SDValue FirstOperand = N->getOperand(0); in performANDCombine()
801 SDValue Mask = N->getOperand(1); in performANDCombine()
802 EVT ValTy = N->getValueType(0); in performANDCombine()
813 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize)) in performANDCombine()
818 // $dst = and ((sra or srl) $src , pos), (2**size - 1) in performANDCombine()
825 Pos = CN->getZExtValue(); in performANDCombine()
845 Pos = CN->getZExtValue(); in performANDCombine()
853 SMSize--; in performANDCombine()
857 // $dst = and $src, (2**size - 1) , if size > 16 in performANDCombine()
861 if (CN->getZExtValue() <= 0xffff) in performANDCombine()
881 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 in performORCombine()
886 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); in performORCombine()
895 !isShiftedMask_64(~CN->getSExtValue(), SMPos0, SMSize0)) in performORCombine()
903 !isShiftedMask_64(CN->getZExtValue(), SMPos1, SMSize1)) in performORCombine()
915 unsigned Shamt = CN->getZExtValue(); in performORCombine()
919 EVT ValTy = N->getValueType(0); in performORCombine()
931 // where mask0 = ((1 << SMSize0) -1) << SMPos0 in performORCombine()
933 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && in performORCombine()
939 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) in performORCombine()
942 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) in performORCombine()
947 if (CN->getSExtValue() & CN1->getSExtValue()) in performORCombine()
951 EVT ValTy = N->getOperand(0)->getValueType(0); in performORCombine()
956 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
959 MipsISD::Ins, DL, N->getValueType(0), in performORCombine()
961 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) in performORCombine()
967 And0->getOperand(0)); in performORCombine()
978 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && in performMADD_MSUBCombine()
979 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) in performMADD_MSUBCombine()
986 if (ROOTNode->getOpcode() == ISD::SUB && in performMADD_MSUBCombine()
987 ROOTNode->getOperand(0).getOpcode() == ISD::MUL) in performMADD_MSUBCombine()
991 if (ROOTNode->getValueType(0).isVector()) in performMADD_MSUBCombine()
1016 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL in performMADD_MSUBCombine()
1017 ? ROOTNode->getOperand(0) in performMADD_MSUBCombine()
1018 : ROOTNode->getOperand(1); in performMADD_MSUBCombine()
1020 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL in performMADD_MSUBCombine()
1021 ? ROOTNode->getOperand(1) in performMADD_MSUBCombine()
1022 : ROOTNode->getOperand(0); in performMADD_MSUBCombine()
1033 // this optimization pre-legalization. in performMADD_MSUBCombine()
1034 SDValue MultLHS = Mult->getOperand(0); in performMADD_MSUBCombine()
1035 SDValue MultRHS = Mult->getOperand(1); in performMADD_MSUBCombine()
1037 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && in performMADD_MSUBCombine()
1038 MultRHS->getOpcode() == ISD::SIGN_EXTEND; in performMADD_MSUBCombine()
1039 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && in performMADD_MSUBCombine()
1040 MultRHS->getOpcode() == ISD::ZERO_EXTEND; in performMADD_MSUBCombine()
1054 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; in performMADD_MSUBCombine()
1058 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), in performMADD_MSUBCombine()
1059 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; in performMADD_MSUBCombine()
1076 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) in performSUBCombine()
1091 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) in performADDCombine()
1098 SDValue Add = N->getOperand(1); in performADDCombine()
1109 EVT ValTy = N->getValueType(0); in performADDCombine()
1112 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), in performADDCombine()
1127 SDValue FirstOperand = N->getOperand(0); in performSHLCombine()
1129 SDValue SecondOperand = N->getOperand(1); in performSHLCombine()
1130 EVT ValTy = N->getValueType(0); in performSHLCombine()
1142 Pos = CN->getZExtValue(); in performSHLCombine()
1152 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize)) in performSHLCombine()
1162 SMSize--; in performSHLCombine()
1172 unsigned Opc = N->getOpcode(); in PerformDAGCombine()
1210 // double-word variants. in hasBitTest()
1212 return C->getAPIntValue().ule(15); in hasBitTest()
1219 assert(((N->getOpcode() == ISD::SHL && in shouldFoldConstantShiftPairToMask()
1220 N->getOperand(0).getOpcode() == ISD::SRL) || in shouldFoldConstantShiftPairToMask()
1221 (N->getOpcode() == ISD::SRL && in shouldFoldConstantShiftPairToMask()
1222 N->getOperand(0).getOpcode() == ISD::SHL)) && in shouldFoldConstantShiftPairToMask()
1223 "Expected shift-shift mask"); in shouldFoldConstantShiftPairToMask()
1225 if (N->getOperand(0).getValueType().isVector()) in shouldFoldConstantShiftPairToMask()
1269 //===----------------------------------------------------------------------===//
1271 //===----------------------------------------------------------------------===//
1273 // addLiveIn - This helper function adds the specified physical register to the
1301 // Use the 32-bit sub-register if this is a 64-bit division. in insertDivByZeroTrap()
1303 MIB->getOperand(0).setSubReg(Mips::sub_32); in insertDivByZeroTrap()
1491 MachineFunction *MF = BB->getParent(); in emitAtomicBinary()
1492 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitAtomicBinary()
1606 // An atomic read-modify-write sequence starts with a linked load in emitAtomicBinary()
1608 // read-modify-write sequence fails if any of the following conditions in emitAtomicBinary()
1613 // implementation-dependent. in emitAtomicBinary()
1622 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); in emitAtomicBinary()
1623 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); in emitAtomicBinary()
1626 BuildMI(*BB, II, DL, TII->get(AtomicOp)) in emitAtomicBinary()
1651 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); in emitSignExtendToI32InReg()
1656 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); in emitSignExtendToI32InReg()
1660 MachineFunction *MF = BB->getParent(); in emitSignExtendToI32InReg()
1661 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitSignExtendToI32InReg()
1666 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg()
1668 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
1669 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
1679 MachineFunction *MF = BB->getParent(); in emitAtomicBinaryPartword()
1680 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitAtomicBinaryPartword()
1786 const BasicBlock *LLVM_BB = BB->getBasicBlock(); in emitAtomicBinaryPartword()
1787 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); in emitAtomicBinaryPartword()
1788 MachineFunction::iterator It = ++BB->getIterator(); in emitAtomicBinaryPartword()
1789 MF->insert(It, exitMBB); in emitAtomicBinaryPartword()
1792 exitMBB->splice(exitMBB->begin(), BB, in emitAtomicBinaryPartword()
1793 std::next(MachineBasicBlock::iterator(MI)), BB->end()); in emitAtomicBinaryPartword()
1794 exitMBB->transferSuccessorsAndUpdatePHIs(BB); in emitAtomicBinaryPartword()
1796 BB->addSuccessor(exitMBB, BranchProbability::getOne()); in emitAtomicBinaryPartword()
1799 // addiu masklsb2,$0,-4 # 0xfffffffc in emitAtomicBinaryPartword()
1809 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) in emitAtomicBinaryPartword()
1810 .addReg(ABI.GetNullPtr()).addImm(-4); in emitAtomicBinaryPartword()
1811 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) in emitAtomicBinaryPartword()
1813 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) in emitAtomicBinaryPartword()
1816 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); in emitAtomicBinaryPartword()
1819 BuildMI(BB, DL, TII->get(Mips::XORi), Off) in emitAtomicBinaryPartword()
1821 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); in emitAtomicBinaryPartword()
1823 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) in emitAtomicBinaryPartword()
1825 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicBinaryPartword()
1827 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); in emitAtomicBinaryPartword()
1828 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1836 BuildMI(BB, DL, TII->get(AtomicOp)) in emitAtomicBinaryPartword()
1875 MachineFunction *MF = BB->getParent(); in emitAtomicCmpSwap()
1876 MachineRegisterInfo &MRI = MF->getRegInfo(); in emitAtomicCmpSwap()
1901 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); in emitAtomicCmpSwap()
1902 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal); in emitAtomicCmpSwap()
1903 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal); in emitAtomicCmpSwap()
1909 BuildMI(*BB, II, DL, TII->get(AtomicOp)) in emitAtomicCmpSwap()
1927 MachineFunction *MF = BB->getParent(); in emitAtomicCmpSwapPartword()
1928 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitAtomicCmpSwapPartword()
1970 const BasicBlock *LLVM_BB = BB->getBasicBlock(); in emitAtomicCmpSwapPartword()
1971 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); in emitAtomicCmpSwapPartword()
1972 MachineFunction::iterator It = ++BB->getIterator(); in emitAtomicCmpSwapPartword()
1973 MF->insert(It, exitMBB); in emitAtomicCmpSwapPartword()
1976 exitMBB->splice(exitMBB->begin(), BB, in emitAtomicCmpSwapPartword()
1977 std::next(MachineBasicBlock::iterator(MI)), BB->end()); in emitAtomicCmpSwapPartword()
1978 exitMBB->transferSuccessorsAndUpdatePHIs(BB); in emitAtomicCmpSwapPartword()
1980 BB->addSuccessor(exitMBB, BranchProbability::getOne()); in emitAtomicCmpSwapPartword()
1983 // addiu masklsb2,$0,-4 # 0xfffffffc in emitAtomicCmpSwapPartword()
1996 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) in emitAtomicCmpSwapPartword()
1997 .addReg(ABI.GetNullPtr()).addImm(-4); in emitAtomicCmpSwapPartword()
1998 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) in emitAtomicCmpSwapPartword()
2000 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) in emitAtomicCmpSwapPartword()
2003 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); in emitAtomicCmpSwapPartword()
2006 BuildMI(BB, DL, TII->get(Mips::XORi), Off) in emitAtomicCmpSwapPartword()
2008 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); in emitAtomicCmpSwapPartword()
2010 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) in emitAtomicCmpSwapPartword()
2012 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicCmpSwapPartword()
2014 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); in emitAtomicCmpSwapPartword()
2015 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) in emitAtomicCmpSwapPartword()
2017 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) in emitAtomicCmpSwapPartword()
2019 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) in emitAtomicCmpSwapPartword()
2021 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) in emitAtomicCmpSwapPartword()
2028 BuildMI(BB, DL, TII->get(AtomicOp)) in emitAtomicCmpSwapPartword()
2061 Mips::CondCode CC = (Mips::CondCode)CCNode->getAsZExtVal(); in lowerBRCOND()
2101 const GlobalValue *GV = N->getGlobal(); in lowerGlobalAddress()
2107 const GlobalObject *GO = GV->getAliaseeObject(); in lowerGlobalAddress()
2108 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) in lowerGlobalAddress()
2128 // * Given all that, we have to use a full got entry for hidden symbols :-( in lowerGlobalAddress()
2129 if (GV->hasLocalLinkage()) in lowerGlobalAddress()
2168 const GlobalValue *GV = GA->getGlobal(); in lowerGlobalTLSAddress()
2262 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), in lowerConstantPool()
2279 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), in lowerVASTART()
2284 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); in lowerVASTART()
2291 EVT VT = Node->getValueType(0); in lowerVAARG()
2292 SDValue Chain = Node->getOperand(0); in lowerVAARG()
2293 SDValue VAListPtr = Node->getOperand(1); in lowerVAARG()
2295 llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne(); in lowerVAARG()
2296 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); in lowerVAARG()
2304 // Re-align the pointer if necessary. in lowerVAARG()
2305 // It should only ever be necessary for 64-bit types on O32 since the minimum in lowerVAARG()
2314 DAG.getConstant(Align.value() - 1, DL, VAList.getValueType())); in lowerVAARG()
2318 DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType())); in lowerVAARG()
2333 // In big-endian mode we must adjust the pointer when the load size is smaller in lowerVAARG()
2339 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; in lowerVAARG()
2356 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it in lowerFCOPYSIGN32()
2407 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y in lowerFCOPYSIGN64()
2408 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X in lowerFCOPYSIGN64()
2410 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); in lowerFCOPYSIGN64()
2418 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, in lowerFCOPYSIGN64()
2425 // (d)srl SrlY, Y, width(Y)-1 in lowerFCOPYSIGN64()
2426 // (d)sll SllY, SrlX, width(Y)-1 in lowerFCOPYSIGN64()
2431 DAG.getConstant(WidthY - 1, DL, MVT::i32)); in lowerFCOPYSIGN64()
2439 DAG.getConstant(WidthX - 1, DL, MVT::i32)); in lowerFCOPYSIGN64()
2460 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it in lowerFABS32()
2527 DAG.getContext()->emitError( in lowerFRAMEADDR()
2548 DAG.getContext()->emitError( in lowerRETURNADDR()
2559 // Return RA, which contains the return address. Mark it an implicit live-in. in lowerRETURNADDR()
2573 MipsFI->setCallsEhReturn(); in lowerEH_RETURN()
2581 // EH_RETURN nodes, so that instructions are emitted back-to-back. in lowerEH_RETURN()
2594 // FIXME: Need pseudo-fence for 'singlethread' fences in lowerATOMIC_FENCE()
2611 // hi = (or (shl hi, shamt) (srl (srl lo, 1), (xor shamt, (VT.bits-1)))) in lowerShiftLeftParts()
2617 DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32)); in lowerShiftLeftParts()
2642 // lo = (or (shl (shl hi, 1), (xor shamt, (VT.bits-1))) (srl lo, shamt)) in lowerShiftRightParts()
2656 DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32)); in lowerShiftRightParts()
2667 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); in lowerShiftRightParts()
2688 SDValue Ptr = LD->getBasePtr(); in createLoadLR()
2689 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); in createLoadLR()
2700 LD->getMemOperand()); in createLoadLR()
2703 // Expand an unaligned 32 or 64-bit integer load node.
2706 EVT MemVT = LD->getMemoryVT(); in lowerLOAD()
2712 if ((LD->getAlign().value() >= (MemVT.getSizeInBits() / 8)) || in lowerLOAD()
2718 ISD::LoadExtType ExtType = LD->getExtensionType(); in lowerLOAD()
2719 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); in lowerLOAD()
2770 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); in createStoreLR()
2771 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); in createStoreLR()
2781 SD->getMemOperand()); in createStoreLR()
2784 // Expand an unaligned 32 or 64-bit integer store node.
2787 SDValue Value = SD->getValue(), Chain = SD->getChain(); in lowerUnalignedIntStore()
2796 if ((VT == MVT::i32) || SD->isTruncatingStore()) { in lowerUnalignedIntStore()
2816 SDValue Val = SD->getValue(); in lowerFP_TO_SINT_STORE()
2825 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), in lowerFP_TO_SINT_STORE()
2826 SD->getPointerInfo(), SD->getAlign(), in lowerFP_TO_SINT_STORE()
2827 SD->getMemOperand()->getFlags()); in lowerFP_TO_SINT_STORE()
2832 EVT MemVT = SD->getMemoryVT(); in lowerSTORE()
2836 (SD->getAlign().value() < (MemVT.getSizeInBits() / 8)) && in lowerSTORE()
2849 EVT ValTy = Op->getValueType(0); in lowerEH_DWARF_CFA()
2865 //===----------------------------------------------------------------------===//
2867 //===----------------------------------------------------------------------===//
2869 //===----------------------------------------------------------------------===//
2872 // ---
2873 // i32 - Passed in A0, A1, A2, A3 and stack
2874 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2876 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2880 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2881 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2883 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2887 //===----------------------------------------------------------------------===//
2940 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); in CC_MipsO32()
3040 //===----------------------------------------------------------------------===//
3042 //===----------------------------------------------------------------------===//
3070 // R_MIPS_CALL* operators (emitted when non-internal functions are called in getOpndList()
3084 // Build a sequence of copy-to-reg nodes chained together with token in getOpndList()
3100 // Add a register mask operand representing the call-preserved registers. in getOpndList()
3103 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); in getOpndList()
3107 StringRef Sym = G->getGlobal()->getName(); in getOpndList()
3108 Function *F = G->getGlobal()->getParent()->getFunction(Sym); in getOpndList()
3109 if (F && F->hasFnAttribute("__Mips16RetHelper")) { in getOpndList()
3140 Node->getNumOperands() < 1 || in AdjustInstrPostInstrSelection()
3141 Node->getOperand(0).getNumOperands() < 2) { in AdjustInstrPostInstrSelection()
3147 const SDValue TargetAddr = Node->getOperand(0).getOperand(1); in AdjustInstrPostInstrSelection()
3152 // since this will cause run-time crashes if the linker replaces the in AdjustInstrPostInstrSelection()
3154 if (!isa<Function>(G->getGlobal())) { in AdjustInstrPostInstrSelection()
3156 << G->getGlobal()->getName() << "\n"); in AdjustInstrPostInstrSelection()
3159 Sym = G->getGlobal()->getName(); in AdjustInstrPostInstrSelection()
3163 Sym = ES->getSymbol(); in AdjustInstrPostInstrSelection()
3169 MachineFunction *MF = MI.getParent()->getParent(); in AdjustInstrPostInstrSelection()
3170 MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym); in AdjustInstrPostInstrSelection()
3177 /// LowerCall - functions arguments are copied from virtual regs to
3232 bool MemcpyInByVal = ES && StringRef(ES->getSymbol()) == "memcpy" && in LowerCall()
3243 ES ? ES->getSymbol() : nullptr); in LowerCall()
3258 InternalLinkage = G->getGlobal()->hasInternalLinkage(); in LowerCall()
3259 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || in LowerCall()
3260 G->getGlobal()->hasPrivateLinkage() || in LowerCall()
3261 G->getGlobal()->hasHiddenVisibility() || in LowerCall()
3262 G->getGlobal()->hasProtectedVisibility()); in LowerCall()
3265 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) in LowerCall()
3275 unsigned StackAlignment = TFL->getStackAlignment(); in LowerCall()
3305 "ByVal args of size 0 should have been ignored by front-end."); in LowerCall()
3308 "Do not tail-call optimize if there is a byval argument."); in LowerCall()
3372 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCall()
3414 // The long-calls feature is ignored in case of PIC. in LowerCall()
3415 // While we do not support -mshared / -mno-shared properly, in LowerCall()
3416 // ignore long-calls in case of -mabicalls too. in LowerCall()
3428 // If the function has long-call/far/near attribute in LowerCall()
3430 if (auto *F = dyn_cast<Function>(N->getGlobal())) { in LowerCall()
3431 if (F->hasFnAttribute("long-call")) in LowerCall()
3433 else if (F->hasFnAttribute("short-call")) in LowerCall()
3445 const GlobalValue *Val = G->getGlobal(); in LowerCall()
3446 InternalLinkage = Val->hasInternalLinkage(); in LowerCall()
3453 FuncInfo->callPtrInfo(MF, Val)); in LowerCall()
3457 FuncInfo->callPtrInfo(MF, Val)); in LowerCall()
3461 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, in LowerCall()
3467 const char *Sym = S->getSymbol(); in LowerCall()
3475 FuncInfo->callPtrInfo(MF, Sym)); in LowerCall()
3479 FuncInfo->callPtrInfo(MF, Sym)); in LowerCall()
3517 /// LowerCallResult - Lower the result values of a call into the
3532 ES ? ES->getSymbol() : nullptr); in LowerCallResult()
3551 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCallResult()
3605 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in UnpackFromArgumentSlot()
3610 // If this is an value smaller than the argument slot size (32-bit for O32, in UnpackFromArgumentSlot()
3611 // 64-bit for N32/N64), it has been promoted in some way to the argument slot in UnpackFromArgumentSlot()
3641 //===----------------------------------------------------------------------===//
3643 //===----------------------------------------------------------------------===//
3644 /// LowerFormalArguments - transform physical registers into virtual registers
3654 MipsFI->setVarArgsFrameIndex(0); in LowerFormalArguments()
3672 MipsFI->setFormalArgInfo(CCInfo.getStackSize(), in LowerFormalArguments()
3681 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx); in LowerFormalArguments()
3695 "ByVal args of size 0 should have been ignored by front-end."); in LowerFormalArguments()
3725 assert(VA.needsCustom() && "Expected custom argument for f64 split"); in LowerFormalArguments()
3740 assert(!VA.needsCustom() && "unexpected custom memory argument"); in LowerFormalArguments()
3774 unsigned Reg = MipsFI->getSRetReturnReg(); in LowerFormalArguments()
3778 MipsFI->setSRetReturnReg(Reg); in LowerFormalArguments()
3799 //===----------------------------------------------------------------------===//
3801 //===----------------------------------------------------------------------===//
3828 MipsFI->setISR(); in LowerInterruptReturn()
3839 // CCValAssign - represent the assignment of in LowerReturn()
3844 // CCState - Info about the registers and stack slot. in LowerReturn()
3893 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerReturn()
3909 unsigned Reg = MipsFI->getSRetReturnReg(); in LowerReturn()
3936 //===----------------------------------------------------------------------===//
3938 //===----------------------------------------------------------------------===//
3940 /// getConstraintType - Given a constraint letter, return the type of
3952 // jump. This will always be $25 for -mabicalls. in getConstraintType()
3988 Type *type = CallOperandVal->getType(); in getSingleConstraintMatchWeight()
3996 if (type->isIntegerTy()) in getSingleConstraintMatchWeight()
4000 if (Subtarget.hasMSA() && type->isVectorTy() && in getSingleConstraintMatchWeight()
4001 type->getPrimitiveSizeInBits().getFixedValue() == 128) in getSingleConstraintMatchWeight()
4003 else if (type->isFloatTy()) in getSingleConstraintMatchWeight()
4009 if (type->isIntegerTy()) in getSingleConstraintMatchWeight()
4016 case 'N': // immediate in the range of -65535 to -1 (inclusive) in getSingleConstraintMatchWeight()
4017 case 'O': // signed 15 bit immediate (+- 16383) in getSingleConstraintMatchWeight()
4030 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
4039 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; in parsePhysicalReg()
4042 Prefix = StringRef(B, I - B); in parsePhysicalReg()
4049 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), in parsePhysicalReg()
4078 RC = TRI->getRegClass(Prefix == "hi" ? in parseRegForInlineAsmConstraint()
4080 return std::make_pair(*(RC->begin()), RC); in parseRegForInlineAsmConstraint()
4102 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); in parseRegForInlineAsmConstraint()
4109 if (Prefix == "$f") { // Parse $f0-$f31. in parseRegForInlineAsmConstraint()
4110 // If the size of FP registers is 64-bit or Reg is an even number, select in parseRegForInlineAsmConstraint()
4111 // the 64-bit register class. Otherwise, select the 32-bit register class. in parseRegForInlineAsmConstraint()
4121 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. in parseRegForInlineAsmConstraint()
4122 RC = TRI->getRegClass(Mips::FCCRegClassID); in parseRegForInlineAsmConstraint()
4123 else if (Prefix == "$w") { // Parse $w0-$w31. in parseRegForInlineAsmConstraint()
4125 } else { // Parse $0-$31. in parseRegForInlineAsmConstraint()
4130 assert(Reg < RC->getNumRegs()); in parseRegForInlineAsmConstraint()
4131 return std::make_pair(*(RC->begin() + Reg), RC); in parseRegForInlineAsmConstraint()
4209 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4229 int64_t Val = C->getSExtValue(); in LowerAsmOperandForConstraint()
4239 int64_t Val = C->getZExtValue(); in LowerAsmOperandForConstraint()
4249 uint64_t Val = (uint64_t)C->getZExtValue(); in LowerAsmOperandForConstraint()
4259 int64_t Val = C->getSExtValue(); in LowerAsmOperandForConstraint()
4266 case 'N': // immediate in the range of -65535 to -1 (inclusive) in LowerAsmOperandForConstraint()
4269 int64_t Val = C->getSExtValue(); in LowerAsmOperandForConstraint()
4270 if ((Val >= -65535) && (Val <= -1)) { in LowerAsmOperandForConstraint()
4279 int64_t Val = C->getSExtValue(); in LowerAsmOperandForConstraint()
4289 int64_t Val = C->getSExtValue(); in LowerAsmOperandForConstraint()
4373 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
4381 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - in copyByValRegs()
4382 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); in copyByValRegs()
4431 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
4439 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { in passByValArg()
4453 // Copy the remainder of the byval argument with sub-word loads and shifts. in passByValArg()
4459 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; in passByValArg()
4479 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; in passByValArg()
4501 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; in passByValArg()
4533 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - in writeVarArgRegs()
4534 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); in writeVarArgRegs()
4540 MipsFI->setVarArgsFrameIndex(FI); in writeVarArgRegs()
4554 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( in writeVarArgRegs()
4566 Alignment = std::min(Alignment, TFL->getStackAlign()); in HandleByVal()
4571 if (State->getCallingConv() != CallingConv::Fast) { in HandleByVal()
4584 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
4591 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); in HandleByVal()
4598 Size -= RegSizeInBytes, ++I, ++NumRegs) in HandleByVal()
4599 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); in HandleByVal()
4602 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); in HandleByVal()
4611 "conditional-move instructions."); in emitPseudoSELECT()
4618 // diamond control-flow pattern. The incoming instruction knows the in emitPseudoSELECT()
4621 const BasicBlock *LLVM_BB = BB->getBasicBlock(); in emitPseudoSELECT()
4622 MachineFunction::iterator It = ++BB->getIterator(); in emitPseudoSELECT()
4629 // fallthrough --> copy0MBB in emitPseudoSELECT()
4631 MachineFunction *F = BB->getParent(); in emitPseudoSELECT()
4632 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); in emitPseudoSELECT()
4633 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); in emitPseudoSELECT()
4634 F->insert(It, copy0MBB); in emitPseudoSELECT()
4635 F->insert(It, sinkMBB); in emitPseudoSELECT()
4638 sinkMBB->splice(sinkMBB->begin(), BB, in emitPseudoSELECT()
4639 std::next(MachineBasicBlock::iterator(MI)), BB->end()); in emitPseudoSELECT()
4640 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); in emitPseudoSELECT()
4643 BB->addSuccessor(copy0MBB); in emitPseudoSELECT()
4644 BB->addSuccessor(sinkMBB); in emitPseudoSELECT()
4648 BuildMI(BB, DL, TII->get(Opc)) in emitPseudoSELECT()
4653 BuildMI(BB, DL, TII->get(Opc)) in emitPseudoSELECT()
4664 // Update machine-CFG edges in emitPseudoSELECT()
4665 BB->addSuccessor(sinkMBB); in emitPseudoSELECT()
4672 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) in emitPseudoSELECT()
4688 "conditional-move instructions."); in emitPseudoD_SELECT()
4695 // conditional-move instruction, it reduces unnecessary branch instructions in emitPseudoD_SELECT()
4698 const BasicBlock *LLVM_BB = BB->getBasicBlock(); in emitPseudoD_SELECT()
4699 MachineFunction::iterator It = ++BB->getIterator(); in emitPseudoD_SELECT()
4706 // fallthrough --> copy0MBB in emitPseudoD_SELECT()
4708 MachineFunction *F = BB->getParent(); in emitPseudoD_SELECT()
4709 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); in emitPseudoD_SELECT()
4710 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); in emitPseudoD_SELECT()
4711 F->insert(It, copy0MBB); in emitPseudoD_SELECT()
4712 F->insert(It, sinkMBB); in emitPseudoD_SELECT()
4715 sinkMBB->splice(sinkMBB->begin(), BB, in emitPseudoD_SELECT()
4716 std::next(MachineBasicBlock::iterator(MI)), BB->end()); in emitPseudoD_SELECT()
4717 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); in emitPseudoD_SELECT()
4720 BB->addSuccessor(copy0MBB); in emitPseudoD_SELECT()
4721 BB->addSuccessor(sinkMBB); in emitPseudoD_SELECT()
4724 BuildMI(BB, DL, TII->get(Mips::BNE)) in emitPseudoD_SELECT()
4734 // Update machine-CFG edges in emitPseudoD_SELECT()
4735 BB->addSuccessor(sinkMBB); in emitPseudoD_SELECT()
4743 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) in emitPseudoD_SELECT()
4748 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg()) in emitPseudoD_SELECT()
4785 MachineFunction *MF = BB->getParent(); in emitLDR_W()
4786 MachineRegisterInfo &MRI = MF->getRegInfo(); in emitLDR_W()
4798 // Mips release 6 can load from adress that is not naturally-aligned. in emitLDR_W()
4799 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_W() local
4800 BuildMI(*BB, I, DL, TII->get(Mips::LW)) in emitLDR_W()
4801 .addDef(Temp) in emitLDR_W()
4804 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); in emitLDR_W()
4811 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef); in emitLDR_W()
4812 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_W()
4817 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) in emitLDR_W()
4822 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); in emitLDR_W()
4831 MachineFunction *MF = BB->getParent(); in emitLDR_D()
4832 MachineRegisterInfo &MRI = MF->getRegInfo(); in emitLDR_D()
4844 // Mips release 6 can load from adress that is not naturally-aligned. in emitLDR_D()
4846 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass); in emitLDR_D() local
4847 BuildMI(*BB, I, DL, TII->get(Mips::LD)) in emitLDR_D()
4848 .addDef(Temp) in emitLDR_D()
4851 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); in emitLDR_D()
4856 BuildMI(*BB, I, DL, TII->get(Mips::LW)) in emitLDR_D()
4860 BuildMI(*BB, I, DL, TII->get(Mips::LW)) in emitLDR_D()
4864 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(Lo); in emitLDR_D()
4865 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) in emitLDR_D()
4880 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(LoUndef); in emitLDR_D()
4881 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_D()
4886 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) in emitLDR_D()
4891 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(HiUndef); in emitLDR_D()
4892 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) in emitLDR_D()
4897 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) in emitLDR_D()
4902 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(LoFull); in emitLDR_D()
4903 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) in emitLDR_D()
4915 MachineFunction *MF = BB->getParent(); in emitSTR_W()
4916 MachineRegisterInfo &MRI = MF->getRegInfo(); in emitSTR_W()
4928 // Mips release 6 can store to adress that is not naturally-aligned. in emitSTR_W()
4931 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(BitcastW).addUse(StoreVal); in emitSTR_W()
4932 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) in emitSTR_W()
4936 BuildMI(*BB, I, DL, TII->get(Mips::SW)) in emitSTR_W()
4944 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) in emitSTR_W()
4948 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) in emitSTR_W()
4952 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) in emitSTR_W()
4965 MachineFunction *MF = BB->getParent(); in emitSTR_D()
4966 MachineRegisterInfo &MRI = MF->getRegInfo(); in emitSTR_D()
4978 // Mips release 6 can store to adress that is not naturally-aligned. in emitSTR_D()
4982 BuildMI(*BB, I, DL, TII->get(Mips::COPY)) in emitSTR_D()
4985 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_D)) in emitSTR_D()
4989 BuildMI(*BB, I, DL, TII->get(Mips::SD)) in emitSTR_D()
4997 BuildMI(*BB, I, DL, TII->get(Mips::COPY)) in emitSTR_D()
5000 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) in emitSTR_D()
5004 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) in emitSTR_D()
5008 BuildMI(*BB, I, DL, TII->get(Mips::SW)) in emitSTR_D()
5012 BuildMI(*BB, I, DL, TII->get(Mips::SW)) in emitSTR_D()
5023 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(Bitcast).addUse(StoreVal); in emitSTR_D()
5024 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) in emitSTR_D()
5028 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) in emitSTR_D()
5032 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) in emitSTR_D()
5036 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) in emitSTR_D()
5040 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) in emitSTR_D()
5044 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) in emitSTR_D()