Lines Matching refs:RightReg
639 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned); in emitCmp() local
640 if (RightReg == 0) in emitCmp()
649 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
655 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
660 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
663 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
667 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
673 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
678 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
681 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
685 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
691 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
741 .addReg(RightReg); in emitCmp()