Lines Matching full:mips
1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
10 /// This file defines the MIPS-specific support for the FastISel class.
74 #define DEBUG_TYPE "mips-fastisel"
300 Opc = Mips::AND; in emitLogicalOp()
303 Opc = Mips::OR; in emitLogicalOp()
306 Opc = Mips::XOR; in emitLogicalOp()
324 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
340 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
341 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::LEA_ADDiu), in fastMaterializeAlloca()
354 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
364 unsigned Opc = Mips::ADDiu; in materialize32BitInt()
365 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
368 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
376 emitInst(Mips::LUi, TmpReg).addImm(Hi); in materialize32BitInt()
377 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
379 emitInst(Mips::LUi, ResultReg).addImm(Hi); in materialize32BitInt()
389 const TargetRegisterClass *RC = &Mips::FGR32RegClass; in materializeFP()
391 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP()
392 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
395 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; in materializeFP()
397 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); in materializeFP()
399 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); in materializeFP()
400 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
410 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeGV()
417 emitInst(Mips::LW, DestReg) in materializeGV()
423 emitInst(Mips::ADDiu, TempReg) in materializeGV()
432 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeExternalCallSym()
434 emitInst(Mips::LW, DestReg) in materializeExternalCallSym()
648 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
649 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
650 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
654 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
655 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
656 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
660 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
663 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
666 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
667 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
668 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
672 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
673 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
674 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
678 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
681 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
684 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
685 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
686 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
690 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
691 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
692 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
710 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; in emitCmp()
711 CondMovOpc = Mips::MOVT_I; in emitCmp()
714 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; in emitCmp()
715 CondMovOpc = Mips::MOVF_I; in emitCmp()
718 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32; in emitCmp()
719 CondMovOpc = Mips::MOVT_I; in emitCmp()
722 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32; in emitCmp()
723 CondMovOpc = Mips::MOVT_I; in emitCmp()
726 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32; in emitCmp()
727 CondMovOpc = Mips::MOVF_I; in emitCmp()
730 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32; in emitCmp()
731 CondMovOpc = Mips::MOVF_I; in emitCmp()
736 Register RegWithZero = createResultReg(&Mips::GPR32RegClass); in emitCmp()
737 Register RegWithOne = createResultReg(&Mips::GPR32RegClass); in emitCmp()
738 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
739 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
740 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) in emitCmp()
744 .addReg(Mips::FCC0) in emitCmp()
759 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
760 Opc = Mips::LW; in emitLoad()
763 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
764 Opc = Mips::LHu; in emitLoad()
767 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
768 Opc = Mips::LBu; in emitLoad()
773 ResultReg = createResultReg(&Mips::FGR32RegClass); in emitLoad()
774 Opc = Mips::LWC1; in emitLoad()
779 ResultReg = createResultReg(&Mips::AFGR64RegClass); in emitLoad()
780 Opc = Mips::LDC1; in emitLoad()
813 Opc = Mips::SB; in emitStore()
816 Opc = Mips::SH; in emitStore()
819 Opc = Mips::SW; in emitStore()
824 Opc = Mips::SWC1; in emitStore()
829 Opc = Mips::SDC1; in emitStore()
953 ZExtCondReg = createResultReg(&Mips::GPR32RegClass); in selectBranch()
970 BuildMI(*BrBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::BGTZ)) in selectBranch()
979 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in selectCmp()
1003 Register DestReg = createResultReg(&Mips::AFGR64RegClass); in selectFPExt()
1004 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg); in selectFPExt()
1025 CondMovOpc = Mips::MOVN_I_I; in selectSelect()
1026 RC = &Mips::GPR32RegClass; in selectSelect()
1028 CondMovOpc = Mips::MOVN_I_S; in selectSelect()
1029 RC = &Mips::FGR32RegClass; in selectSelect()
1031 CondMovOpc = Mips::MOVN_I_D32; in selectSelect()
1032 RC = &Mips::AFGR64RegClass; in selectSelect()
1045 Register ZExtCondReg = createResultReg(&Mips::GPR32RegClass); in selectSelect()
1080 Register DestReg = createResultReg(&Mips::FGR32RegClass); in selectFPTrunc()
1084 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg); in selectFPTrunc()
1118 Register DestReg = createResultReg(&Mips::GPR32RegClass); in selectFPToInt()
1119 Register TempReg = createResultReg(&Mips::FGR32RegClass); in selectFPToInt()
1120 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32; in selectFPToInt()
1124 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
1143 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0); in processCallArgs()
1154 VA.convertToReg(Mips::F12); in processCallArgs()
1157 VA.convertToReg(Mips::D6_64); in processCallArgs()
1159 VA.convertToReg(Mips::D6); in processCallArgs()
1164 VA.convertToReg(Mips::F14); in processCallArgs()
1167 VA.convertToReg(Mips::D7_64); in processCallArgs()
1169 VA.convertToReg(Mips::D7); in processCallArgs()
1178 VA.convertToReg(Mips::A0); in processCallArgs()
1181 VA.convertToReg(Mips::A1); in processCallArgs()
1184 VA.convertToReg(Mips::A2); in processCallArgs()
1187 VA.convertToReg(Mips::A3); in processCallArgs()
1228 llvm_unreachable("Mips does not use custom args."); in processCallArgs()
1233 // from the AArch64 port and should be essentially fine for Mips too. in processCallArgs()
1254 Addr.setReg(Mips::SP); in processCallArgs()
1273 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0); in finishCall()
1325 std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2, in fastLowerArguments()
1326 Mips::A3}}; in fastLowerArguments()
1327 std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}}; in fastLowerArguments()
1328 std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}}; in fastLowerArguments()
1383 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++); in fastLowerArguments()
1403 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++); in fastLowerArguments()
1420 Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++); in fastLowerArguments()
1439 Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++); in fastLowerArguments()
1551 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress); in fastLowerCall()
1553 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::JALR), in fastLowerCall()
1554 Mips::RA).addReg(Mips::T9); in fastLowerCall()
1594 Register DestReg = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1599 emitInst(Mips::WSBH, DestReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1605 R = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1609 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1610 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1611 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[1]).addImm(0xFF); in fastLowerIntrinsicCall()
1612 emitInst(Mips::OR, DestReg).addReg(TempReg[0]).addReg(TempReg[2]); in fastLowerIntrinsicCall()
1618 Register TempReg = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1619 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1620 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16); in fastLowerIntrinsicCall()
1626 R = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1631 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1632 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1633 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00); in fastLowerIntrinsicCall()
1634 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]); in fastLowerIntrinsicCall()
1636 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00); in fastLowerIntrinsicCall()
1637 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); in fastLowerIntrinsicCall()
1639 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1640 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]); in fastLowerIntrinsicCall()
1641 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]); in fastLowerIntrinsicCall()
1765 MachineInstrBuilder MIB = emitInst(Mips::RetRA); in selectRet()
1815 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in selectIntExt()
1836 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitIntSExt32r1()
1837 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1838 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
1848 emitInst(Mips::SEB, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1851 emitInst(Mips::SEH, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1884 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm); in emitIntZExt()
1904 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in emitIntExt()
1924 DivOpc = Mips::SDIV; in selectDivRem()
1928 DivOpc = Mips::UDIV; in selectDivRem()
1938 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
1940 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in selectDivRem()
1945 ? Mips::MFHI in selectDivRem()
1946 : Mips::MFLO; in selectDivRem()
1959 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in selectShift()
1971 Register TempReg = createResultReg(&Mips::GPR32RegClass); in selectShift()
1990 Opcode = Mips::SLL; in selectShift()
1993 Opcode = Mips::SRA; in selectShift()
1996 Opcode = Mips::SRL; in selectShift()
2013 Opcode = Mips::SLLV; in selectShift()
2016 Opcode = Mips::SRAV; in selectShift()
2019 Opcode = Mips::SRLV; in selectShift()
2097 Register TempReg = createResultReg(&Mips::GPR32RegClass); in getRegEnsuringSimpleIntegerWidening()
2108 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass); in simplifyAddress()
2109 Register DestReg = createResultReg(&Mips::GPR32RegClass); in simplifyAddress()
2110 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()
2125 if (MachineInstOpcode == Mips::MUL) { in fastEmitInst_rr()
2133 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2134 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
2143 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo, in createFastISel()