Lines Matching refs:Mips
84 unsigned ZERO = Mips::ZERO; in expandAtomicCmpSwapSubword()
85 unsigned BNE = Mips::BNE; in expandAtomicCmpSwapSubword()
86 unsigned BEQ = Mips::BEQ; in expandAtomicCmpSwapSubword()
88 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH; in expandAtomicCmpSwapSubword()
91 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicCmpSwapSubword()
92 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicCmpSwapSubword()
93 BNE = STI->hasMips32r6() ? Mips::BNEC_MMR6 : Mips::BNE_MM; in expandAtomicCmpSwapSubword()
94 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicCmpSwapSubword()
96 LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicCmpSwapSubword()
97 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicCmpSwapSubword()
98 SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in expandAtomicCmpSwapSubword()
99 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); in expandAtomicCmpSwapSubword()
146 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2) in expandAtomicCmpSwapSubword()
157 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch) in expandAtomicCmpSwapSubword()
160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch) in expandAtomicCmpSwapSubword()
175 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicCmpSwapSubword()
182 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I16_POSTRA ? 16 : 24; in expandAtomicCmpSwapSubword()
183 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest) in expandAtomicCmpSwapSubword()
186 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest) in expandAtomicCmpSwapSubword()
207 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I32_POSTRA ? 4 : 8; in expandAtomicCmpSwap()
217 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicCmpSwap()
218 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicCmpSwap()
219 BNE = STI->hasMips32r6() ? Mips::BNEC_MMR6 : Mips::BNE_MM; in expandAtomicCmpSwap()
220 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicCmpSwap()
223 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicCmpSwap()
224 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicCmpSwap()
226 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in expandAtomicCmpSwap()
227 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); in expandAtomicCmpSwap()
228 BNE = Mips::BNE; in expandAtomicCmpSwap()
229 BEQ = Mips::BEQ; in expandAtomicCmpSwap()
232 ZERO = Mips::ZERO; in expandAtomicCmpSwap()
233 MOVE = Mips::OR; in expandAtomicCmpSwap()
235 LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; in expandAtomicCmpSwap()
236 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicCmpSwap()
237 ZERO = Mips::ZERO_64; in expandAtomicCmpSwap()
238 BNE = Mips::BNE64; in expandAtomicCmpSwap()
239 BEQ = Mips::BEQ64; in expandAtomicCmpSwap()
240 MOVE = Mips::OR64; in expandAtomicCmpSwap()
312 unsigned BEQ = Mips::BEQ; in expandAtomicBinOpSubword()
313 unsigned SEOp = Mips::SEH; in expandAtomicBinOpSubword()
316 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicBinOpSubword()
317 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicBinOpSubword()
318 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicBinOpSubword()
319 SLT = Mips::SLT_MM; in expandAtomicBinOpSubword()
320 SLTu = Mips::SLTu_MM; in expandAtomicBinOpSubword()
321 OR = STI->hasMips32r6() ? Mips::OR_MMR6 : Mips::OR_MM; in expandAtomicBinOpSubword()
322 MOVN = Mips::MOVN_I_MM; in expandAtomicBinOpSubword()
323 MOVZ = Mips::MOVZ_I_MM; in expandAtomicBinOpSubword()
324 SELNEZ = STI->hasMips32r6() ? Mips::SELNEZ_MMR6 : Mips::SELNEZ; in expandAtomicBinOpSubword()
325 SELEQZ = STI->hasMips32r6() ? Mips::SELEQZ_MMR6 : Mips::SELEQZ; in expandAtomicBinOpSubword()
327 LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicBinOpSubword()
328 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicBinOpSubword()
329 SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in expandAtomicBinOpSubword()
330 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); in expandAtomicBinOpSubword()
331 SLT = Mips::SLT; in expandAtomicBinOpSubword()
332 SLTu = Mips::SLTu; in expandAtomicBinOpSubword()
333 OR = Mips::OR; in expandAtomicBinOpSubword()
334 MOVN = Mips::MOVN_I_I; in expandAtomicBinOpSubword()
335 MOVZ = Mips::MOVZ_I_I; in expandAtomicBinOpSubword()
336 SELNEZ = Mips::SELNEZ; in expandAtomicBinOpSubword()
337 SELEQZ = Mips::SELEQZ; in expandAtomicBinOpSubword()
349 case Mips::ATOMIC_LOAD_NAND_I8_POSTRA: in expandAtomicBinOpSubword()
350 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
352 case Mips::ATOMIC_LOAD_NAND_I16_POSTRA: in expandAtomicBinOpSubword()
355 case Mips::ATOMIC_SWAP_I8_POSTRA: in expandAtomicBinOpSubword()
356 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
358 case Mips::ATOMIC_SWAP_I16_POSTRA: in expandAtomicBinOpSubword()
361 case Mips::ATOMIC_LOAD_ADD_I8_POSTRA: in expandAtomicBinOpSubword()
362 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
364 case Mips::ATOMIC_LOAD_ADD_I16_POSTRA: in expandAtomicBinOpSubword()
365 Opcode = Mips::ADDu; in expandAtomicBinOpSubword()
367 case Mips::ATOMIC_LOAD_SUB_I8_POSTRA: in expandAtomicBinOpSubword()
368 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
370 case Mips::ATOMIC_LOAD_SUB_I16_POSTRA: in expandAtomicBinOpSubword()
371 Opcode = Mips::SUBu; in expandAtomicBinOpSubword()
373 case Mips::ATOMIC_LOAD_AND_I8_POSTRA: in expandAtomicBinOpSubword()
374 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
376 case Mips::ATOMIC_LOAD_AND_I16_POSTRA: in expandAtomicBinOpSubword()
377 Opcode = Mips::AND; in expandAtomicBinOpSubword()
379 case Mips::ATOMIC_LOAD_OR_I8_POSTRA: in expandAtomicBinOpSubword()
380 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
382 case Mips::ATOMIC_LOAD_OR_I16_POSTRA: in expandAtomicBinOpSubword()
383 Opcode = Mips::OR; in expandAtomicBinOpSubword()
385 case Mips::ATOMIC_LOAD_XOR_I8_POSTRA: in expandAtomicBinOpSubword()
386 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
388 case Mips::ATOMIC_LOAD_XOR_I16_POSTRA: in expandAtomicBinOpSubword()
389 Opcode = Mips::XOR; in expandAtomicBinOpSubword()
391 case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: in expandAtomicBinOpSubword()
392 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
396 case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: in expandAtomicBinOpSubword()
400 case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: in expandAtomicBinOpSubword()
401 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
404 case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: in expandAtomicBinOpSubword()
407 case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: in expandAtomicBinOpSubword()
408 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
412 case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: in expandAtomicBinOpSubword()
416 case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: in expandAtomicBinOpSubword()
417 SEOp = Mips::SEB; in expandAtomicBinOpSubword()
420 case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: in expandAtomicBinOpSubword()
459 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes) in expandAtomicBinOpSubword()
462 BuildMI(loopMBB, DL, TII->get(Mips::NOR), BinOpRes) in expandAtomicBinOpSubword()
463 .addReg(Mips::ZERO) in expandAtomicBinOpSubword()
465 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes) in expandAtomicBinOpSubword()
479 BuildMI(loopMBB, DL, TII->get(Mips::SRAV), StoreVal) in expandAtomicBinOpSubword()
483 const unsigned OpMask = SEOp == Mips::SEH ? 0xffff : 0xff; in expandAtomicBinOpSubword()
484 BuildMI(loopMBB, DL, TII->get(Mips::ANDi), StoreVal) in expandAtomicBinOpSubword()
490 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword()
491 const unsigned SROp = IsUnsigned ? Mips::SRL : Mips::SRA; in expandAtomicBinOpSubword()
492 BuildMI(loopMBB, DL, TII->get(Mips::SLL), StoreVal) in expandAtomicBinOpSubword()
499 BuildMI(loopMBB, DL, TII->get(Mips::OR), Dest) in expandAtomicBinOpSubword()
500 .addReg(Mips::ZERO) in expandAtomicBinOpSubword()
503 BuildMI(loopMBB, DL, TII->get(Mips::SLLV), StoreVal) in expandAtomicBinOpSubword()
536 .addReg(Mips::ZERO); in expandAtomicBinOpSubword()
544 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes) in expandAtomicBinOpSubword()
554 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes) in expandAtomicBinOpSubword()
559 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes) in expandAtomicBinOpSubword()
568 BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal) in expandAtomicBinOpSubword()
570 BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal) in expandAtomicBinOpSubword()
575 .addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB); in expandAtomicBinOpSubword()
584 BuildMI(sinkMBB, DL, TII->get(Mips::AND), Dest).addReg(OldVal).addReg(Mask); in expandAtomicBinOpSubword()
585 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicBinOpSubword()
592 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword()
593 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest) in expandAtomicBinOpSubword()
596 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest) in expandAtomicBinOpSubword()
626 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicBinOp()
627 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicBinOp()
628 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicBinOp()
629 SLT = Mips::SLT_MM; in expandAtomicBinOp()
630 SLTu = Mips::SLTu_MM; in expandAtomicBinOp()
631 OR = STI->hasMips32r6() ? Mips::OR_MMR6 : Mips::OR_MM; in expandAtomicBinOp()
632 MOVN = Mips::MOVN_I_MM; in expandAtomicBinOp()
633 MOVZ = Mips::MOVZ_I_MM; in expandAtomicBinOp()
634 SELNEZ = STI->hasMips32r6() ? Mips::SELNEZ_MMR6 : Mips::SELNEZ; in expandAtomicBinOp()
635 SELEQZ = STI->hasMips32r6() ? Mips::SELEQZ_MMR6 : Mips::SELEQZ; in expandAtomicBinOp()
638 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicBinOp()
639 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicBinOp()
641 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) in expandAtomicBinOp()
642 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); in expandAtomicBinOp()
643 BEQ = Mips::BEQ; in expandAtomicBinOp()
644 SLT = Mips::SLT; in expandAtomicBinOp()
645 SLTu = Mips::SLTu; in expandAtomicBinOp()
646 OR = Mips::OR; in expandAtomicBinOp()
647 MOVN = Mips::MOVN_I_I; in expandAtomicBinOp()
648 MOVZ = Mips::MOVZ_I_I; in expandAtomicBinOp()
649 SELNEZ = Mips::SELNEZ; in expandAtomicBinOp()
650 SELEQZ = Mips::SELEQZ; in expandAtomicBinOp()
653 ZERO = Mips::ZERO; in expandAtomicBinOp()
655 LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; in expandAtomicBinOp()
656 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicBinOp()
657 ZERO = Mips::ZERO_64; in expandAtomicBinOp()
658 BEQ = Mips::BEQ64; in expandAtomicBinOp()
659 SLT = Mips::SLT64; in expandAtomicBinOp()
660 SLTu = Mips::SLTu64; in expandAtomicBinOp()
661 OR = Mips::OR64; in expandAtomicBinOp()
662 MOVN = Mips::MOVN_I64_I64; in expandAtomicBinOp()
663 MOVZ = Mips::MOVZ_I64_I64; in expandAtomicBinOp()
664 SELNEZ = Mips::SELNEZ64; in expandAtomicBinOp()
665 SELEQZ = Mips::SELEQZ64; in expandAtomicBinOp()
684 case Mips::ATOMIC_LOAD_ADD_I32_POSTRA: in expandAtomicBinOp()
685 Opcode = Mips::ADDu; in expandAtomicBinOp()
687 case Mips::ATOMIC_LOAD_SUB_I32_POSTRA: in expandAtomicBinOp()
688 Opcode = Mips::SUBu; in expandAtomicBinOp()
690 case Mips::ATOMIC_LOAD_AND_I32_POSTRA: in expandAtomicBinOp()
691 Opcode = Mips::AND; in expandAtomicBinOp()
693 case Mips::ATOMIC_LOAD_OR_I32_POSTRA: in expandAtomicBinOp()
694 Opcode = Mips::OR; in expandAtomicBinOp()
696 case Mips::ATOMIC_LOAD_XOR_I32_POSTRA: in expandAtomicBinOp()
697 Opcode = Mips::XOR; in expandAtomicBinOp()
699 case Mips::ATOMIC_LOAD_NAND_I32_POSTRA: in expandAtomicBinOp()
701 AND = Mips::AND; in expandAtomicBinOp()
702 NOR = Mips::NOR; in expandAtomicBinOp()
704 case Mips::ATOMIC_SWAP_I32_POSTRA: in expandAtomicBinOp()
707 case Mips::ATOMIC_LOAD_ADD_I64_POSTRA: in expandAtomicBinOp()
708 Opcode = Mips::DADDu; in expandAtomicBinOp()
710 case Mips::ATOMIC_LOAD_SUB_I64_POSTRA: in expandAtomicBinOp()
711 Opcode = Mips::DSUBu; in expandAtomicBinOp()
713 case Mips::ATOMIC_LOAD_AND_I64_POSTRA: in expandAtomicBinOp()
714 Opcode = Mips::AND64; in expandAtomicBinOp()
716 case Mips::ATOMIC_LOAD_OR_I64_POSTRA: in expandAtomicBinOp()
717 Opcode = Mips::OR64; in expandAtomicBinOp()
719 case Mips::ATOMIC_LOAD_XOR_I64_POSTRA: in expandAtomicBinOp()
720 Opcode = Mips::XOR64; in expandAtomicBinOp()
722 case Mips::ATOMIC_LOAD_NAND_I64_POSTRA: in expandAtomicBinOp()
724 AND = Mips::AND64; in expandAtomicBinOp()
725 NOR = Mips::NOR64; in expandAtomicBinOp()
727 case Mips::ATOMIC_SWAP_I64_POSTRA: in expandAtomicBinOp()
730 case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA: in expandAtomicBinOp()
731 case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA: in expandAtomicBinOp()
734 case Mips::ATOMIC_LOAD_MIN_I32_POSTRA: in expandAtomicBinOp()
735 case Mips::ATOMIC_LOAD_MIN_I64_POSTRA: in expandAtomicBinOp()
738 case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA: in expandAtomicBinOp()
739 case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: in expandAtomicBinOp()
742 case Mips::ATOMIC_LOAD_MAX_I32_POSTRA: in expandAtomicBinOp()
743 case Mips::ATOMIC_LOAD_MAX_I64_POSTRA: in expandAtomicBinOp()
776 (Size == 8) ? STI->getRegisterInfo()->getSubReg(Scratch2, Mips::sub_32) in expandAtomicBinOp()
859 case Mips::ATOMIC_CMP_SWAP_I32_POSTRA: in expandMI()
860 case Mips::ATOMIC_CMP_SWAP_I64_POSTRA: in expandMI()
862 case Mips::ATOMIC_CMP_SWAP_I8_POSTRA: in expandMI()
863 case Mips::ATOMIC_CMP_SWAP_I16_POSTRA: in expandMI()
865 case Mips::ATOMIC_SWAP_I8_POSTRA: in expandMI()
866 case Mips::ATOMIC_SWAP_I16_POSTRA: in expandMI()
867 case Mips::ATOMIC_LOAD_NAND_I8_POSTRA: in expandMI()
868 case Mips::ATOMIC_LOAD_NAND_I16_POSTRA: in expandMI()
869 case Mips::ATOMIC_LOAD_ADD_I8_POSTRA: in expandMI()
870 case Mips::ATOMIC_LOAD_ADD_I16_POSTRA: in expandMI()
871 case Mips::ATOMIC_LOAD_SUB_I8_POSTRA: in expandMI()
872 case Mips::ATOMIC_LOAD_SUB_I16_POSTRA: in expandMI()
873 case Mips::ATOMIC_LOAD_AND_I8_POSTRA: in expandMI()
874 case Mips::ATOMIC_LOAD_AND_I16_POSTRA: in expandMI()
875 case Mips::ATOMIC_LOAD_OR_I8_POSTRA: in expandMI()
876 case Mips::ATOMIC_LOAD_OR_I16_POSTRA: in expandMI()
877 case Mips::ATOMIC_LOAD_XOR_I8_POSTRA: in expandMI()
878 case Mips::ATOMIC_LOAD_XOR_I16_POSTRA: in expandMI()
879 case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: in expandMI()
880 case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: in expandMI()
881 case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: in expandMI()
882 case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: in expandMI()
883 case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: in expandMI()
884 case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: in expandMI()
885 case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: in expandMI()
886 case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: in expandMI()
888 case Mips::ATOMIC_LOAD_ADD_I32_POSTRA: in expandMI()
889 case Mips::ATOMIC_LOAD_SUB_I32_POSTRA: in expandMI()
890 case Mips::ATOMIC_LOAD_AND_I32_POSTRA: in expandMI()
891 case Mips::ATOMIC_LOAD_OR_I32_POSTRA: in expandMI()
892 case Mips::ATOMIC_LOAD_XOR_I32_POSTRA: in expandMI()
893 case Mips::ATOMIC_LOAD_NAND_I32_POSTRA: in expandMI()
894 case Mips::ATOMIC_SWAP_I32_POSTRA: in expandMI()
895 case Mips::ATOMIC_LOAD_MIN_I32_POSTRA: in expandMI()
896 case Mips::ATOMIC_LOAD_MAX_I32_POSTRA: in expandMI()
897 case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA: in expandMI()
898 case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA: in expandMI()
900 case Mips::ATOMIC_LOAD_ADD_I64_POSTRA: in expandMI()
901 case Mips::ATOMIC_LOAD_SUB_I64_POSTRA: in expandMI()
902 case Mips::ATOMIC_LOAD_AND_I64_POSTRA: in expandMI()
903 case Mips::ATOMIC_LOAD_OR_I64_POSTRA: in expandMI()
904 case Mips::ATOMIC_LOAD_XOR_I64_POSTRA: in expandMI()
905 case Mips::ATOMIC_LOAD_NAND_I64_POSTRA: in expandMI()
906 case Mips::ATOMIC_SWAP_I64_POSTRA: in expandMI()
907 case Mips::ATOMIC_LOAD_MIN_I64_POSTRA: in expandMI()
908 case Mips::ATOMIC_LOAD_MAX_I64_POSTRA: in expandMI()
909 case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA: in expandMI()
910 case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: in expandMI()