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1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 /// CCIfSubtarget - Match if the current subtarget has a feature F.
23 /// For example, this is true for i32's that were lowered from soft-float.
25     : CCIf<"!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)",
28 /// Match if the original argument (before lowering) was a 128-bit float (i.e.
31     : CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", A>;
37     : CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)", A>;
42                 "->WasOriginalRetVectorFloat(ValNo)", A>;
46     : CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == "
49 // For soft-float, f128 values are returned in A0_64 rather than V1_64.
54 // For hard-float, f128 values are returned as a pair of f64's rather than a
68 // tablegen-erated code.
76 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
85   // size and 4-byte aligned.
89   // size and 8-byte aligned.
121 //===----------------------------------------------------------------------===//
123 //===----------------------------------------------------------------------===//
138   // All integers (except soft-float integers) are promoted to 64-bit.
141   // The only i32's we have left are soft-float arguments.
163   // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
175   // All integers are promoted to 64-bit.
183   // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
191   // This presents us with a problem for the calling convention since hard-float
192   // still needs to pass them in FPU registers, and soft-float needs to use $v0,
194   // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on
195   // whether the result was originally an f128 into the tablegen-erated code.
197   // f128 should only occur for the N64 ABI where long double is 128-bit. On
202   // both little and big-endian targets. When passing in registers, this
203   // requires that big-endian targets shift the value into the upper bits.
220 //===----------------------------------------------------------------------===//
222 //===----------------------------------------------------------------------===//
224   // f64 arguments are passed in double-precision floating pointer registers.
240   // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
250   // f64 arguments are passed in double-precision floating pointer registers.
256   // Stack parameter slots for i64 and f64 are 64-bit doublewords and
257   // 8-byte aligned.
280   // f32 arguments are passed in single-precision floating pointer registers.
285   // Don't use odd numbered single-precision registers for -mno-odd-spreg.
289   // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
296 //===----------------------------------------------------------------------===//
298 //===----------------------------------------------------------------------===//
326   // f128 needs to be handled similarly to f32 and f64 on hard-float. However,
329   // This presents us with a problem for the calling convention since hard-float
331   // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on
332   // whether the argument was originally an f128 into the tablegen-erated code.
334   // f128 should only occur for the N64 ABI where long double is 128-bit. On
358 //===----------------------------------------------------------------------===//
359 // Callee-saved register lists.
360 //===----------------------------------------------------------------------===//