120     TmpInst0.setOpcode(Mips::JALR64);  in emitPseudoIndirectBranch()
125       TmpInst0.setOpcode(Mips::JRC16_MMR6);  in emitPseudoIndirectBranch()
127       TmpInst0.setOpcode(Mips::JALR);  in emitPseudoIndirectBranch()
132     TmpInst0.setOpcode(Mips::JR_MM);  in emitPseudoIndirectBranch()
135     TmpInst0.setOpcode(Mips::JR);  in emitPseudoIndirectBranch()
141     unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;  in emitPseudoIndirectBranch()
204   if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {  in emitInstruction()
208   if (Opc == Mips::CONSTPOOL_ENTRY) {  in emitInstruction()
236   case Mips::PATCHABLE_FUNCTION_ENTER:  in emitInstruction()
239   case Mips::PATCHABLE_FUNCTION_EXIT:  in emitInstruction()
242   case Mips::PATCHABLE_TAIL_CALL:  in emitInstruction()
264     if (I->getOpcode() == Mips::PseudoReturn ||  in emitInstruction()
265         I->getOpcode() == Mips::PseudoReturn64 ||  in emitInstruction()
266         I->getOpcode() == Mips::PseudoIndirectBranch ||  in emitInstruction()
267         I->getOpcode() == Mips::PseudoIndirectBranch64 ||  in emitInstruction()
268         I->getOpcode() == Mips::TAILCALLREG ||  in emitInstruction()
269         I->getOpcode() == Mips::TAILCALLREG64) {  in emitInstruction()
338   unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;  in printSavedRegsBitmask()
339   unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;  in printSavedRegsBitmask()
340   unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;  in printSavedRegsBitmask()
350     if (Mips::FGR32RegClass.contains(Reg)) {  in printSavedRegsBitmask()
353     } else if (Mips::AFGR64RegClass.contains(Reg)) {  in printSavedRegsBitmask()
357     } else if (Mips::GPR32RegClass.contains(Reg))  in printSavedRegsBitmask()
571       if (w != Mips::NoRegister) {  in PrintAsmOperand()
698   case Mips::SWM32_MM:  in printMemOperand()
699   case Mips::LWM32_MM:  in printMemOperand()
723   O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());  in printFCCOperand()
825   I.setOpcode(Mips::JAL);  in EmitJal()
848   if (Opcode == Mips::MTC1) {  in EmitInstrRegReg()
888   unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;  in EmitSwapFPIntParams()
891     EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);  in EmitSwapFPIntParams()
894     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);  in EmitSwapFPIntParams()
897     EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);  in EmitSwapFPIntParams()
898     EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);  in EmitSwapFPIntParams()
901     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
904     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
905     EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);  in EmitSwapFPIntParams()
908     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
909     EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);  in EmitSwapFPIntParams()
921   unsigned MovOpc = Mips::MFC1;  in EmitSwapFPIntRetval()
924     EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);  in EmitSwapFPIntRetval()
927     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
930     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
933     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
934     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);  in EmitSwapFPIntRetval()
1063   EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);  in EmitFPCallStub()
1078   EmitInstrReg(*STI, Mips::JR, Mips::S2);  in EmitFPCallStub()
1180   EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)  in EmitSled()
1181                                    .addReg(Mips::ZERO)  in EmitSled()
1182                                    .addReg(Mips::ZERO)  in EmitSled()
1186     EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)  in EmitSled()
1187                                      .addReg(Mips::ZERO)  in EmitSled()
1188                                      .addReg(Mips::ZERO)  in EmitSled()
1195                    MCInstBuilder(Mips::ADDiu)  in EmitSled()
1196                        .addReg(Mips::T9)  in EmitSled()
1197                        .addReg(Mips::T9)  in EmitSled()
1264   return (Opcode == Mips::LONG_BRANCH_LUi  in isLongBranchPseudo()
1265           || Opcode == Mips::LONG_BRANCH_LUi2Op  in isLongBranchPseudo()
1266           || Opcode == Mips::LONG_BRANCH_LUi2Op_64  in isLongBranchPseudo()
1267           || Opcode == Mips::LONG_BRANCH_ADDiu  in isLongBranchPseudo()
1268           || Opcode == Mips::LONG_BRANCH_ADDiu2Op  in isLongBranchPseudo()
1269           || Opcode == Mips::LONG_BRANCH_DADDiu  in isLongBranchPseudo()
1270           || Opcode == Mips::LONG_BRANCH_DADDiu2Op);  in isLongBranchPseudo()