Lines Matching full:rt
215 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
216 !strconcat(opstr, "\t$rt, $addr"),
217 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
220 string Constraints = "$src = $rt";
228 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
229 !strconcat(opstr, "\t$rt, $addr"),
230 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
239 MicroMipsInst16<(outs RO1:$rd1, RO2:$rd2), (ins RO3:$rs, RO3:$rt),
240 !strconcat(opstr, "\t$rd1, $rd2, $rs, $rt"), [],
248 : InstSE<(outs), (ins GPR32Opnd:$rt, GPR32Opnd:$rt2, mem_simm12:$addr),
249 !strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> {
256 : InstSE<(outs GPR32Opnd:$rt, GPR32Opnd:$rt2), (ins mem_simm12:$addr),
257 !strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> {
264 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
265 !strconcat(opstr, "\t$rt, $addr"), [], II_LL, FrmI> {
271 InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
272 !strconcat(opstr, "\t$rt, $addr"), [], II_LLE, FrmI> {
279 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
280 !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
283 let Constraints = "$rt = $dst";
287 InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
288 !strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> {
292 let Constraints = "$rt = $dst";
297 InstSE<(outs RO:$rt), (ins MO:$addr),
298 !strconcat(opstr, "\t$rt, $addr"),
299 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
308 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
309 !strconcat(opstr, "\t$rd, $rs, $rt"),
310 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
322 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
323 !strconcat(opstr, "\t$rt, $rs"),
324 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
326 let Constraints = "$rt = $dst";
330 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
331 !strconcat(opstr, "\t$rt, $rs"),
332 [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
336 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
337 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
341 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
342 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
350 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
351 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
358 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
359 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
367 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
368 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
375 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
376 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
546 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
547 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
553 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
554 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
560 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
561 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
567 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
568 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
598 InstSE<(outs DstRC:$rt), (ins SrcRC:$rs, uimm3:$sel),
599 !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {
605 InstSE<(outs DstRC:$rs), (ins SrcRC:$rt, uimm3:$sel),
606 !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {
704 def CFC2_MM : InstSE<(outs GPR32Opnd:$rt), (ins COP2Opnd:$impl),
705 "cfc2\t$rt, $impl", [], II_CFC2, FrmFR, "cfc2">,
707 def CTC2_MM : InstSE<(outs COP2Opnd:$impl), (ins GPR32Opnd:$rt),
708 "ctc2\t$rt, $impl", [], II_CTC2, FrmFR, "ctc2">,
793 (rotr GPR32Opnd:$rt, immZExt5:$shamt))];
798 (rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];
889 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
890 !strconcat(instr_asm, "\t$rt, $addr")> ;
893 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
894 !strconcat(instr_asm, "\t$rt, $addr")> ;
1264 def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>,
1332 def : MipsInstAlias<"neg $rt, $rs",
1333 (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1335 def : MipsInstAlias<"neg $rt",
1336 (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1338 def : MipsInstAlias<"negu $rt, $rs",
1339 (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1341 def : MipsInstAlias<"negu $rt",
1342 (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1344 def : MipsInstAlias<"teq $rs, $rt",
1345 (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1346 def : MipsInstAlias<"tge $rs, $rt",
1347 (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1348 def : MipsInstAlias<"tgeu $rs, $rt",
1349 (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1350 def : MipsInstAlias<"tlt $rs, $rt",
1351 (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1352 def : MipsInstAlias<"tltu $rs, $rt",
1353 (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1354 def : MipsInstAlias<"tne $rs, $rt",
1355 (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1357 "sgt $rd, $rs, $rt",
1358 (SLT_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1360 "sgt $rs, $rt",
1361 (SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1363 "sgtu $rd, $rs, $rt",
1364 (SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1366 "sgtu $rs, $rt",
1367 (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1368 def : MipsInstAlias<"sll $rd, $rt, $rs",
1369 (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1370 def : MipsInstAlias<"sra $rd, $rt, $rs",
1371 (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1372 def : MipsInstAlias<"srl $rd, $rt, $rs",
1373 (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1374 def : MipsInstAlias<"sll $rd, $rt",
1375 (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1376 def : MipsInstAlias<"sra $rd, $rt",
1377 (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1378 def : MipsInstAlias<"srl $rd, $rt",
1379 (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1386 def : MipsInstAlias<"rotr $rt, $imm",
1387 (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
1406 def : MipsInstAlias<"not $rt, $rs",
1407 (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1409 def : MipsInstAlias<"not $rt",
1410 (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
1431 def : MipsInstAlias<"rdhwr $rt, $rs",
1432 (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1437 def : MipsInstAlias<"mfgc0 $rt, $rs",
1438 (MFGC0_MM GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1440 def : MipsInstAlias<"mfhgc0 $rt, $rs",
1441 (MFHGC0_MM GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1443 def : MipsInstAlias<"mtgc0 $rt, $rs",
1444 (MTGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1446 def : MipsInstAlias<"mthgc0 $rt, $rs",
1447 (MTHGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1449 def : MipsInstAlias<"sw $rt, $offset",
1450 (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), 1>,