Lines Matching refs:STI
39 static bool isMicroMips(const MCSubtargetInfo *STI) { in isMicroMips() argument
40 return STI->hasFeature(Mips::FeatureMicroMips); in isMicroMips()
43 static bool isMips32r6(const MCSubtargetInfo *STI) { in isMips32r6() argument
44 return STI->hasFeature(Mips::FeatureMips32r6); in isMips32r6()
141 const MCSubtargetInfo *STI) { in emitDirectiveCpRestore() argument
176 const MCSubtargetInfo *STI) { in emitR() argument
181 getStreamer().emitInstruction(TmpInst, *STI); in emitR()
185 SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitRX() argument
191 getStreamer().emitInstruction(TmpInst, *STI); in emitRX()
195 SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitRI() argument
196 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
200 SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitRR() argument
201 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
205 SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitII() argument
211 getStreamer().emitInstruction(TmpInst, *STI); in emitII()
216 const MCSubtargetInfo *STI) { in emitRRX() argument
223 getStreamer().emitInstruction(TmpInst, *STI); in emitRRX()
228 const MCSubtargetInfo *STI) { in emitRRR() argument
229 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
234 const MCSubtargetInfo *STI) { in emitRRRX() argument
242 getStreamer().emitInstruction(TmpInst, *STI); in emitRRRX()
247 const MCSubtargetInfo *STI) { in emitRRI() argument
248 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
254 const MCSubtargetInfo *STI) { in emitRRIII() argument
263 getStreamer().emitInstruction(TmpInst, *STI); in emitRRIII()
268 const MCSubtargetInfo *STI) { in emitAddu() argument
270 STI); in emitAddu()
275 const MCSubtargetInfo *STI) { in emitDSLL() argument
277 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
281 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
285 const MCSubtargetInfo *STI) { in emitEmptyDelaySlot() argument
288 if (isMicroMips(STI) && hasShortDelaySlot) { in emitEmptyDelaySlot()
289 Opc = isMips32r6(STI) ? Mips::MOVE16_MMR6 : Mips::MOVE16_MM; in emitEmptyDelaySlot()
290 emitRR(Opc, Mips::ZERO, Mips::ZERO, IDLoc, STI); in emitEmptyDelaySlot()
294 if (isMicroMips(STI)) in emitEmptyDelaySlot()
295 Opc = isMips32r6(STI) ? Mips::SLL_MMR6 : Mips::SLL_MM; in emitEmptyDelaySlot()
297 emitRRI(Opc, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in emitEmptyDelaySlot()
300 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) { in emitNop() argument
301 if (isMicroMips(STI)) in emitNop()
302 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI); in emitNop()
304 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in emitNop()
309 const MCSubtargetInfo *STI) { in emitGPRestore() argument
310 emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI); in emitGPRestore()
317 const MCSubtargetInfo *STI) { in emitStoreWithImmOffset() argument
319 emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI); in emitStoreWithImmOffset()
340 emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI); in emitStoreWithImmOffset()
342 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI); in emitStoreWithImmOffset()
344 emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI); in emitStoreWithImmOffset()
354 const MCSubtargetInfo *STI) { in emitLoadWithImmOffset() argument
356 emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI); in emitLoadWithImmOffset()
376 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI); in emitLoadWithImmOffset()
378 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
380 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI); in emitLoadWithImmOffset()
700 const MCSubtargetInfo *STI) { in emitDirectiveCpRestore() argument
701 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI); in emitDirectiveCpRestore()
801 const MCSubtargetInfo &STI) in MipsTargetELFStreamer() argument
802 : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) { in MipsTargetELFStreamer()
815 const FeatureBitset &Features = STI.getFeatureBits(); in MipsTargetELFStreamer()
836 STI.getTargetTriple().getArch() == Triple::ArchType::mipsel || in MipsTargetELFStreamer()
837 STI.getTargetTriple().getArch() == Triple::ArchType::mips in MipsTargetELFStreamer()
920 S.emitCodeAlignment(Alignment, &STI, Alignment.value()); in finish()
926 const FeatureBitset &Features = STI.getFeatureBits(); in finish()
1147 emitAddu(RegNo, RegNo, GPReg, getABI().IsN64(), &STI); in emitDirectiveCpAdd()
1182 getStreamer().emitInstruction(TmpInst, STI); in emitDirectiveCpLoad()
1195 getStreamer().emitInstruction(TmpInst, STI); in emitDirectiveCpLoad()
1203 getStreamer().emitInstruction(TmpInst, STI); in emitDirectiveCpLoad()
1215 const MCSubtargetInfo *STI) { in emitDirectiveCpRestore() argument
1216 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI); in emitDirectiveCpRestore()
1230 STI); in emitDirectiveCpRestore()
1250 emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI); in emitDirectiveCpsetup()
1253 emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI); in emitDirectiveCpsetup()
1264 emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI); in emitDirectiveCpsetup()
1268 &STI); in emitDirectiveCpsetup()
1272 emitRRR(Mips::ADDu, GPReg, GPReg, RegNo, SMLoc(), &STI); in emitDirectiveCpsetup()
1274 emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI); in emitDirectiveCpsetup()
1296 getStreamer().emitInstruction(Inst, STI); in emitDirectiveCpreturn()