3021         TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, DstReg,  in loadAndAddSymbolAddress()
3026         TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg,  in loadAndAddSymbolAddress()
3066       TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg,  in loadAndAddSymbolAddress()
3070         TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,  in loadAndAddSymbolAddress()
3133     TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, GPReg,  in loadAndAddSymbolAddress()
3137       TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,  in loadAndAddSymbolAddress()
3183       TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,  in loadAndAddSymbolAddress()
3186       TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),  in loadAndAddSymbolAddress()
3189       TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),  in loadAndAddSymbolAddress()
3211       TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,  in loadAndAddSymbolAddress()
3213       TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),  in loadAndAddSymbolAddress()
3233       TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,  in loadAndAddSymbolAddress()
3236       TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,  in loadAndAddSymbolAddress()
3239       TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,  in loadAndAddSymbolAddress()
3277   TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),  in loadAndAddSymbolAddress()
3367       TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr),  in emitPartialAddress()
3370       TOut.emitRRX(Mips::LD, ATReg, GPReg, MCOperand::createExpr(GotExpr),  in emitPartialAddress()
3399       TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,  in emitPartialAddress()
3402       TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),  in emitPartialAddress()
3493   TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr),  in expandLoadSingleImmToFPR()
3551   TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,  in expandLoadDoubleImmToGPR()
3630   TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg,  in expandLoadDoubleImmToFPR()
3720       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,  in expandBranchImm()
3724       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,  in expandBranchImm()
3738       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg,  in expandBranchImm()
3742       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);  in expandBranchImm()
3782       TOut.emitRRX(OpCode, DstReg, TmpReg, Off, IDLoc, STI);  in expandMem16Inst()
3852         TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HigherOperand, IDLoc, STI);  in expandMem16Inst()
3854         TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HiOperand, IDLoc, STI);  in expandMem16Inst()
3909       TOut.emitRRX(OpCode, DstReg, TmpReg, MCOperand::createImm(0), IDLoc, STI);  in expandMem9Inst()
4125       TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,  in expandCondBranches()
4132       TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,  in expandCondBranches()
4157       TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,  in expandCondBranches()
4175       TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE,  in expandCondBranches()
4217   TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL)  in expandCondBranches()
4349     TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);  in expandDivRem()
4380   TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI);  in expandDivRem()
4393     TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI);  in expandDivRem()
5277     TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI);  in expandMulO()
5314     TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI);  in expandMulOU()
5375     TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandLoadStoreDMacro()
5376     TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);  in expandLoadStoreDMacro()
5378     TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);  in expandLoadStoreDMacro()
5379     TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandLoadStoreDMacro()
5422   TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandStoreDM1Macro()
5423   TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);  in expandStoreDM1Macro()