2060       if (Inst.getOperand(1).getReg() == Mips::ZERO ||  in processInstruction()
2086     if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||  in processInstruction()
2088       if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||  in processInstruction()
2101     BInst.addOperand(MCOperand::createReg(Mips::ZERO));  in processInstruction()
2102     BInst.addOperand(MCOperand::createReg(Mips::ZERO));  in processInstruction()
2977   bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO &&  in loadAndAddSymbolAddress()
3297   case Mips::ZERO: return Mips::AT;  in nextReg()
3328   case Mips::RA:   return Mips::ZERO;  in nextReg()
3459   unsigned TmpReg = Mips::ZERO;  in expandLoadSingleImmToFPR()
3467     if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister,  in expandLoadSingleImmToFPR()
3576   unsigned TmpReg = Mips::ZERO;  in expandLoadDoubleImmToFPR()
3586       if (TmpReg != Mips::ZERO &&  in expandLoadDoubleImmToFPR()
3594     if (TmpReg != Mips::ZERO &&  in expandLoadDoubleImmToFPR()
3600       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3604       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3648     Inst.addOperand(MCOperand::createReg(Mips::ZERO));  in expandUncondBranchMMPseudo()
3649     Inst.addOperand(MCOperand::createReg(Mips::ZERO));  in expandUncondBranchMMPseudo()
3665       Inst.addOperand(MCOperand::createReg(Mips::ZERO));  in expandUncondBranchMMPseudo()
3666       Inst.addOperand(MCOperand::createReg(Mips::ZERO));  in expandUncondBranchMMPseudo()
3720       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,  in expandBranchImm()
3722       TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);  in expandBranchImm()
3724       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,  in expandBranchImm()
3740       TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);  in expandBranchImm()
3805     if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)  in expandMem16Inst()
3856         if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)  in expandMem16Inst()
3862         if (BaseReg != Mips::ZERO)  in expandMem16Inst()
4096   bool IsTrgRegZero = (TrgReg == Mips::ZERO);  in expandCondBranches()
4097   bool IsSrcRegZero = (SrcReg == Mips::ZERO);  in expandCondBranches()
4103       TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),  in expandCondBranches()
4108       TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),  in expandCondBranches()
4114       TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),  in expandCondBranches()
4120       TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),  in expandCondBranches()
4125       TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,  in expandCondBranches()
4132       TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,  in expandCondBranches()
4157       TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,  in expandCondBranches()
4176                    IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO,  in expandCondBranches()
4219                ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,  in expandCondBranches()
4268     ZeroReg = Mips::ZERO;  in expandDivRem()
4302       TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);  in expandDivRem()
4322   if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {  in expandDivRem()
4333   if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) {  in expandDivRem()
4595     TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);  in expandUxw()
4946       TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);  in expandRotation()
4977     TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);  in expandRotation()
5071       TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);  in expandDRotation()
5102     TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);  in expandDRotation()
5216     TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);  in expandAbs()
5219   TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);  in expandAbs()
5307     TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI);  in expandMulOU()
5314     TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI);  in expandMulOU()
5443   if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {  in expandSeq()
5449   unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;  in expandSeq()
5474   if (SrcReg == Mips::ZERO) {  in expandSeqI()
5524   if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {  in expandSne()
5526     TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);  in expandSne()
5530   unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;  in expandSne()
5531   TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI);  in expandSne()
5551     TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI);  in expandSneI()
5555   if (SrcReg == Mips::ZERO) {  in expandSneI()
5573     TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);  in expandSneI()
5586   TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);  in expandSneI()
5599           return Mips::ZERO;  in getRegisterForMxtrDSP()
5649     case Mips::F0:  return Mips::ZERO;  in getRegisterForMxtrFP()
5688     case Mips::COP00:  return Mips::ZERO;  in getRegisterForMxtrC0()
5849     if (Inst.getOperand(1).getReg() == Mips::ZERO ||  in checkTargetMatchPredicate()
5903     if (Inst.getOperand(0).getReg() == Mips::ZERO ||  in checkTargetMatchPredicate()
5919     if (Inst.getOperand(0).getReg() == Mips::ZERO ||  in checkTargetMatchPredicate()
5922     if (Inst.getOperand(1).getReg() == Mips::ZERO ||  in checkTargetMatchPredicate()