Lines Matching refs:IDLoc
177 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
221 MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
225 bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
229 bool Is32BitImm, bool IsAddress, SMLoc IDLoc,
233 unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
236 bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym);
238 bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
241 bool expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
243 bool expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
245 bool expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
247 bool expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc,
252 SMLoc IDLoc, MCStreamer &Out,
255 bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
258 void expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
260 void expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
263 bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
266 bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
269 bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
272 bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
275 bool expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
279 bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
282 bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out,
285 bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
288 bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
291 bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
294 bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
297 bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
300 bool expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
303 bool expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
306 bool expandRotation(MCInst &Inst, SMLoc IDLoc,
308 bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
310 bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
312 bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
315 bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
318 bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
321 bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
324 bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
327 bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
330 bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
333 bool expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
336 bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
339 bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
342 bool expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
345 bool expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
348 bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
351 bool expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
441 bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
1872 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, in processInstruction() argument
1880 Inst.setLoc(IDLoc); in processInstruction()
1904 return Error(IDLoc, "branch target out of range"); in processInstruction()
1907 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1934 return Error(IDLoc, "branch target out of range"); in processInstruction()
1937 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1950 return Error(IDLoc, "branch target out of range"); in processInstruction()
1952 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1963 return Error(IDLoc, "branch target out of range"); in processInstruction()
1965 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1974 return Error(IDLoc, "branch target out of range"); in processInstruction()
1976 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1987 return Error(IDLoc, "branch target out of range"); in processInstruction()
1989 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1998 Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a " in processInstruction()
2018 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2022 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2035 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2038 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2062 Warning(IDLoc, "dividing zero by zero"); in processInstruction()
2064 Warning(IDLoc, "division by zero"); in processInstruction()
2090 Warning(IDLoc, "dividing zero by zero"); in processInstruction()
2092 Warning(IDLoc, "division by zero"); in processInstruction()
2110 warnIfNoMacro(IDLoc); in processInstruction()
2117 return Error(IDLoc, "jal doesn't support multiple symbols in PIC mode"); in processInstruction()
2124 !isGP64bit(), IDLoc, Out, STI)) in processInstruction()
2143 getContext(), IDLoc); in processInstruction()
2147 RelocJalrExpr, IDLoc, *STI); in processInstruction()
2161 expandMem9Inst(Inst, IDLoc, Out, STI, MCID.mayLoad()); in processInstruction()
2164 expandMem16Inst(Inst, IDLoc, Out, STI, MCID.mayLoad()); in processInstruction()
2190 IDLoc, STI); in processInstruction()
2209 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2213 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2219 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2222 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2227 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2230 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2235 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2239 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2244 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2249 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2254 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2257 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2263 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2266 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2273 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2276 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2283 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2286 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2291 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2294 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2299 return Error(IDLoc, "invalid operand for instruction"); in processInstruction()
2314 return Error(IDLoc, "invalid operand for instruction"); in processInstruction()
2334 TOut.emitEmptyDelaySlot(false, IDLoc, STI); in processInstruction()
2360 tryExpandInstruction(Inst, IDLoc, Out, STI); in processInstruction()
2400 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI); in processInstruction()
2412 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, in processInstruction()
2416 TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI); in processInstruction()
2418 Warning(IDLoc, "no .cprestore used in PIC mode"); in processInstruction()
2426 SMLoc IDLoc = SMLoc(); in onEndOfFile() local
2429 TOut.emitEmptyDelaySlot(false, IDLoc, STI); in onEndOfFile()
2436 MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in tryExpandInstruction() argument
2442 return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2444 return expandLoadImm(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2453 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, in tryExpandInstruction()
2466 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc, in tryExpandInstruction()
2472 return expandUncondBranchMMPseudo(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2476 return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2480 return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2485 return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2518 return expandCondBranches(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2523 return expandDivRem(Inst, IDLoc, Out, STI, false, true) ? MER_Fail in tryExpandInstruction()
2529 return expandDivRem(Inst, IDLoc, Out, STI, true, true) ? MER_Fail in tryExpandInstruction()
2535 return expandDivRem(Inst, IDLoc, Out, STI, false, false) ? MER_Fail in tryExpandInstruction()
2541 return expandDivRem(Inst, IDLoc, Out, STI, true, false) ? MER_Fail in tryExpandInstruction()
2544 return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2547 return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2550 return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2554 return expandLoadSingleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2557 return expandLoadSingleImmToFPR(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2560 return expandLoadDoubleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2563 return expandLoadDoubleImmToFPR(Inst, true, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2566 return expandLoadDoubleImmToFPR(Inst, false, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2570 return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2572 return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2574 return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2577 return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2580 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2583 return expandSge(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2588 return expandSgeImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2593 return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2596 return expandSle(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2601 return expandSleImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2607 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2613 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2623 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2635 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2641 return expandRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2644 return expandRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2647 return expandDRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2650 return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2652 return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2655 return expandMulImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2658 return expandMulO(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2661 return expandMulOU(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2663 return expandDMULMacro(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2666 return expandLoadStoreDMacro(Inst, IDLoc, Out, STI, in tryExpandInstruction()
2671 return expandStoreDM1Macro(Inst, IDLoc, Out, STI) in tryExpandInstruction()
2675 return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2677 return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2679 return expandSne(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2681 return expandSneI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2691 return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2694 return expandSaaAddr(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2698 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, in expandJalWithRegs() argument
2705 JalrInst.setLoc(IDLoc); in expandJalWithRegs()
2738 TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst), IDLoc, in expandJalWithRegs()
2761 bool IsAddress, SMLoc IDLoc, MCStreamer &Out, in loadImmediate() argument
2766 Error(IDLoc, "instruction requires a 64-bit architecture"); in loadImmediate()
2777 Error(IDLoc, "instruction requires a 32-bit immediate"); in loadImmediate()
2794 unsigned ATReg = getATReg(IDLoc); in loadImmediate()
2808 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2812 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2819 TmpReg = getATReg(IDLoc); in loadImmediate()
2824 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2826 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2831 warnIfNoMacro(IDLoc); in loadImmediate()
2839 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2840 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2842 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2848 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2849 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in loadImmediate()
2851 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2853 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2857 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI); in loadImmediate()
2859 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2861 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2867 Error(IDLoc, "instruction requires a 32-bit immediate"); in loadImmediate()
2880 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
2881 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()
2884 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2889 warnIfNoMacro(IDLoc); in loadImmediate()
2897 IDLoc, Out, STI)) in loadImmediate()
2907 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI); in loadImmediate()
2908 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI); in loadImmediate()
2918 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI); in loadImmediate()
2921 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2926 bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, in expandLoadImm() argument
2934 Is32BitImm, false, IDLoc, Out, STI)) in expandLoadImm()
2942 bool Is32BitAddress, SMLoc IDLoc, in expandLoadAddress() argument
2947 Warning(IDLoc, "la used to load 64-bit address"); in expandLoadAddress()
2954 Error(IDLoc, "instruction requires a 64-bit architecture"); in expandLoadAddress()
2960 Is32BitAddress, IDLoc, Out, STI); in expandLoadAddress()
2968 IDLoc, Out, STI); in expandLoadAddress()
2973 bool Is32BitSym, SMLoc IDLoc, in loadAndAddSymbolAddress() argument
2979 warnIfNoMacro(IDLoc); in loadAndAddSymbolAddress()
2984 Error(IDLoc, "expected relocatable expression"); in loadAndAddSymbolAddress()
2988 Error(IDLoc, "expected relocatable expression with only one symbol"); in loadAndAddSymbolAddress()
3017 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc, in loadAndAddSymbolAddress()
3020 IDLoc, STI); in loadAndAddSymbolAddress()
3022 MCOperand::createExpr(CallLoExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3027 MCOperand::createExpr(CallExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3038 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
3062 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(CallHiExpr), IDLoc, in loadAndAddSymbolAddress()
3065 IDLoc, STI); in loadAndAddSymbolAddress()
3067 MCOperand::createExpr(CallLoExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3073 IDLoc, STI); in loadAndAddSymbolAddress()
3077 IDLoc, STI); in loadAndAddSymbolAddress()
3102 Error(IDLoc, "macro instruction uses large offset, which is not " in loadAndAddSymbolAddress()
3134 MCOperand::createExpr(GotExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3138 MCOperand::createExpr(LoExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3142 IDLoc, STI); in loadAndAddSymbolAddress()
3171 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
3181 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3184 MCOperand::createExpr(HigherExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3185 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3187 IDLoc, STI); in loadAndAddSymbolAddress()
3188 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3190 IDLoc, STI); in loadAndAddSymbolAddress()
3191 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3194 } else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) { in loadAndAddSymbolAddress()
3195 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
3208 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3210 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3212 MCOperand::createExpr(HigherExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3214 IDLoc, STI); in loadAndAddSymbolAddress()
3215 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
3216 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI); in loadAndAddSymbolAddress()
3218 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3222 (canUseATReg() && DstReg == getATReg(IDLoc))) { in loadAndAddSymbolAddress()
3231 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3234 MCOperand::createExpr(HigherExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3235 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3237 MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3238 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3240 MCOperand::createExpr(LoExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3242 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3250 reportParseError(IDLoc, in loadAndAddSymbolAddress()
3270 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
3276 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3278 IDLoc, STI); in loadAndAddSymbolAddress()
3281 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3354 bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, in emitPartialAddress() argument
3356 unsigned ATReg = getATReg(IDLoc); in emitPartialAddress()
3368 IDLoc, STI); in emitPartialAddress()
3371 IDLoc, STI); in emitPartialAddress()
3386 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in emitPartialAddress()
3397 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in emitPartialAddress()
3400 MCOperand::createExpr(HigherExpr), IDLoc, STI); in emitPartialAddress()
3401 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in emitPartialAddress()
3403 IDLoc, STI); in emitPartialAddress()
3404 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in emitPartialAddress()
3428 bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, in expandLoadSingleImmToGPR() argument
3440 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, in expandLoadSingleImmToGPR()
3444 bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, in expandLoadSingleImmToFPR() argument
3461 TmpReg = getATReg(IDLoc); in expandLoadSingleImmToFPR()
3468 true, false, IDLoc, Out, STI)) in expandLoadSingleImmToFPR()
3470 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3487 getStreamer().emitLabel(Sym, IDLoc); in expandLoadSingleImmToFPR()
3491 if (emitPartialAddress(TOut, IDLoc, Sym)) in expandLoadSingleImmToFPR()
3494 IDLoc, STI); in expandLoadSingleImmToFPR()
3498 bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, in expandLoadDoubleImmToGPR() argument
3514 IDLoc, Out, STI)) in expandLoadDoubleImmToGPR()
3518 IDLoc, Out, STI)) in expandLoadDoubleImmToGPR()
3522 IDLoc, Out, STI)) in expandLoadDoubleImmToGPR()
3539 getStreamer().emitLabel(Sym, IDLoc); in expandLoadDoubleImmToGPR()
3544 unsigned TmpReg = getATReg(IDLoc); in expandLoadDoubleImmToGPR()
3548 if (emitPartialAddress(TOut, IDLoc, Sym)) in expandLoadDoubleImmToGPR()
3552 MCOperand::createExpr(LoExpr), IDLoc, STI); in expandLoadDoubleImmToGPR()
3555 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
3557 TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
3558 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI); in expandLoadDoubleImmToGPR()
3564 SMLoc IDLoc, MCStreamer &Out, in expandLoadDoubleImmToFPR() argument
3578 TmpReg = getATReg(IDLoc); in expandLoadDoubleImmToFPR()
3587 loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc, in expandLoadDoubleImmToFPR()
3590 TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3596 IDLoc, Out, STI)) in expandLoadDoubleImmToFPR()
3600 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3601 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3603 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3604 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3622 getStreamer().emitLabel(Sym, IDLoc); in expandLoadDoubleImmToFPR()
3627 if (emitPartialAddress(TOut, IDLoc, Sym)) in expandLoadDoubleImmToFPR()
3631 MCOperand::createExpr(LoExpr), IDLoc, STI); in expandLoadDoubleImmToFPR()
3636 bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, in expandUncondBranchMMPseudo() argument
3660 return Error(IDLoc, "branch target out of range"); in expandUncondBranchMMPseudo()
3662 return Error(IDLoc, "branch to misaligned address"); in expandUncondBranchMMPseudo()
3676 TOut.emitEmptyDelaySlot(true, IDLoc, STI); in expandUncondBranchMMPseudo()
3681 bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandBranchImm() argument
3721 MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI); in expandBranchImm()
3722 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in expandBranchImm()
3724 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, in expandBranchImm()
3727 warnIfNoMacro(IDLoc); in expandBranchImm()
3729 unsigned ATReg = getATReg(IDLoc); in expandBranchImm()
3734 IDLoc, Out, STI)) in expandBranchImm()
3739 MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI); in expandBranchImm()
3740 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in expandBranchImm()
3742 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI); in expandBranchImm()
3747 void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMem16Inst() argument
3775 TmpReg = getATReg(IDLoc); in expandMem16Inst()
3782 TOut.emitRRX(OpCode, DstReg, TmpReg, Off, IDLoc, STI); in expandMem16Inst()
3784 TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, Off, IDLoc, STI); in expandMem16Inst()
3801 IDLoc, Out, STI)) in expandMem16Inst()
3807 TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
3822 Error(IDLoc, "expected relocatable expression"); in expandMem16Inst()
3826 Error(IDLoc, "expected relocatable expression with only one symbol"); in expandMem16Inst()
3831 !ABI.ArePtrs64bit(), IDLoc, Out, STI); in expandMem16Inst()
3851 TOut.emitRX(Mips::LUi, TmpReg, HighestOperand, IDLoc, STI); in expandMem16Inst()
3852 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HigherOperand, IDLoc, STI); in expandMem16Inst()
3853 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3854 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HiOperand, IDLoc, STI); in expandMem16Inst()
3855 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3857 TOut.emitRRR(Mips::DADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
3861 TOut.emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI); in expandMem16Inst()
3863 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
3874 void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMem9Inst() argument
3902 TmpReg = getATReg(IDLoc); in expandMem9Inst()
3909 TOut.emitRRX(OpCode, DstReg, TmpReg, MCOperand::createImm(0), IDLoc, STI); in expandMem9Inst()
3912 IDLoc, STI); in expandMem9Inst()
3917 IDLoc, Out, STI); in expandMem9Inst()
3924 !ABI.ArePtrs64bit(), IDLoc, Out, STI); in expandMem9Inst()
3932 bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, in expandLoadStoreMultiple() argument
3961 bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, in expandCondBranches() argument
3978 warnIfNoMacro(IDLoc); in expandCondBranches()
3981 TrgReg = getATReg(IDLoc); in expandCondBranches()
4039 false, IDLoc, Out, STI)) in expandCondBranches()
4104 IDLoc, STI); in expandCondBranches()
4109 IDLoc, STI); in expandCondBranches()
4110 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
4115 IDLoc, STI); in expandCondBranches()
4116 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
4121 IDLoc, STI); in expandCondBranches()
4126 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
4133 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
4134 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
4158 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
4159 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
4177 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
4185 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
4191 unsigned ATRegNum = getATReg(IDLoc); in expandCondBranches()
4196 warnIfNoMacro(IDLoc); in expandCondBranches()
4215 ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI); in expandCondBranches()
4219 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, in expandCondBranches()
4232 bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandDivRem() argument
4237 warnIfNoMacro(IDLoc); in expandDivRem()
4286 unsigned ATReg = getATReg(IDLoc); in expandDivRem()
4292 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4294 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4299 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
4302 TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI); in expandDivRem()
4305 TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI); in expandDivRem()
4311 TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI); in expandDivRem()
4312 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4324 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4327 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4334 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); in expandDivRem()
4344 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4349 TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI); in expandDivRem()
4352 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); in expandDivRem()
4355 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4361 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4365 unsigned ATReg = getATReg(IDLoc); in expandDivRem()
4372 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem()
4380 TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
4383 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI); in expandDivRem()
4384 TOut.emitDSLL(ATReg, ATReg, 63, IDLoc, STI); in expandDivRem()
4386 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI); in expandDivRem()
4390 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI); in expandDivRem()
4393 TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
4394 TOut.emitNop(IDLoc, STI); in expandDivRem()
4395 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI); in expandDivRem()
4399 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4404 SMLoc IDLoc, MCStreamer &Out, in expandTrunc() argument
4417 unsigned ATReg = getATReg(IDLoc); in expandTrunc()
4420 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4421 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4422 TOut.emitNop(IDLoc, STI); in expandTrunc()
4423 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI); in expandTrunc()
4424 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI); in expandTrunc()
4425 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI); in expandTrunc()
4426 TOut.emitNop(IDLoc, STI); in expandTrunc()
4429 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4430 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI); in expandTrunc()
4431 TOut.emitNop(IDLoc, STI); in expandTrunc()
4437 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4442 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, in expandUlh() argument
4445 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); in expandUlh()
4462 warnIfNoMacro(IDLoc); in expandUlh()
4463 unsigned ATReg = getATReg(IDLoc); in expandUlh()
4470 IDLoc, Out, STI)) in expandUlh()
4486 FirstOffset, IDLoc, STI); in expandUlh()
4487 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI); in expandUlh()
4488 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI); in expandUlh()
4489 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUlh()
4494 bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandUsh() argument
4497 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); in expandUsh()
4512 warnIfNoMacro(IDLoc); in expandUsh()
4513 unsigned ATReg = getATReg(IDLoc); in expandUsh()
4520 IDLoc, Out, STI)) in expandUsh()
4530 TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI); in expandUsh()
4531 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4532 TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI); in expandUsh()
4533 TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI); in expandUsh()
4534 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4535 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUsh()
4537 TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI); in expandUsh()
4538 TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI); in expandUsh()
4539 TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI); in expandUsh()
4545 bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandUxw() argument
4548 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); in expandUxw()
4574 warnIfNoMacro(IDLoc); in expandUxw()
4575 TmpReg = getATReg(IDLoc); in expandUxw()
4582 IDLoc, Out, STI)) in expandUxw()
4591 TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI); in expandUxw()
4592 TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI); in expandUxw()
4595 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI); in expandUxw()
4600 bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSge() argument
4614 warnIfNoMacro(IDLoc); in expandSge()
4628 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSge()
4629 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSge()
4634 bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSgeImm() argument
4648 warnIfNoMacro(IDLoc); in expandSgeImm()
4668 TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI); in expandSgeImm()
4669 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4680 false, IDLoc, Out, STI)) in expandSgeImm()
4683 TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI); in expandSgeImm()
4684 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4690 bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSgtImm() argument
4705 warnIfNoMacro(IDLoc); in expandSgtImm()
4728 false, IDLoc, Out, STI)) in expandSgtImm()
4732 TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI); in expandSgtImm()
4737 bool MipsAsmParser::expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSle() argument
4751 warnIfNoMacro(IDLoc); in expandSle()
4765 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI); in expandSle()
4766 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSle()
4771 bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSleImm() argument
4785 warnIfNoMacro(IDLoc); in expandSleImm()
4810 false, IDLoc, Out, STI)) in expandSleImm()
4813 TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI); in expandSleImm()
4814 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSleImm()
4819 bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, in expandAliasImmediate() argument
4918 TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI); in expandAliasImmediate()
4920 TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI); in expandAliasImmediate()
4926 bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandRotation() argument
4988 bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc, in expandRotationImm() argument
5051 bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandDRotation() argument
5113 bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc, in expandDRotationImm() argument
5208 bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandAbs() argument
5214 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI); in expandAbs()
5216 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI); in expandAbs()
5218 TOut.emitEmptyDelaySlot(false, IDLoc, STI); in expandAbs()
5219 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI); in expandAbs()
5224 bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMulImm() argument
5232 ATReg = getATReg(IDLoc); in expandMulImm()
5236 loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, in expandMulImm()
5240 SrcReg, ATReg, IDLoc, STI); in expandMulImm()
5242 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulImm()
5247 bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMulO() argument
5260 SrcReg, TmpReg, IDLoc, STI); in expandMulO()
5262 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5265 DstReg, DstReg, 0x1F, IDLoc, STI); in expandMulO()
5267 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulO()
5270 TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI); in expandMulO()
5277 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI); in expandMulO()
5279 TOut.emitNop(IDLoc, STI); in expandMulO()
5280 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); in expandMulO()
5284 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5289 bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMulOU() argument
5297 ATReg = getATReg(IDLoc); in expandMulOU()
5302 SrcReg, TmpReg, IDLoc, STI); in expandMulOU()
5304 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulOU()
5305 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulOU()
5307 TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI); in expandMulOU()
5314 TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI); in expandMulOU()
5316 TOut.emitNop(IDLoc, STI); in expandMulOU()
5317 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); in expandMulOU()
5325 bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandDMULMacro() argument
5332 TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI); in expandDMULMacro()
5333 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandDMULMacro()
5343 bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, in expandLoadStoreDMacro() argument
5350 warnIfNoMacro(IDLoc); in expandLoadStoreDMacro()
5360 warnIfRegIndexIsAT(FirstReg, IDLoc); in expandLoadStoreDMacro()
5375 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); in expandLoadStoreDMacro()
5376 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); in expandLoadStoreDMacro()
5378 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); in expandLoadStoreDMacro()
5379 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); in expandLoadStoreDMacro()
5391 bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, in expandStoreDM1Macro() argument
5397 warnIfNoMacro(IDLoc); in expandStoreDM1Macro()
5407 warnIfRegIndexIsAT(FirstReg, IDLoc); in expandStoreDM1Macro()
5422 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); in expandStoreDM1Macro()
5423 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); in expandStoreDM1Macro()
5428 bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSeq() argument
5441 warnIfNoMacro(IDLoc); in expandSeq()
5444 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5445 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeq()
5450 TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI); in expandSeq()
5454 bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSeqI() argument
5467 warnIfNoMacro(IDLoc); in expandSeqI()
5470 TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI); in expandSeqI()
5475 Warning(IDLoc, "comparison is always false"); in expandSeqI()
5477 DstReg, SrcReg, SrcReg, IDLoc, STI); in expandSeqI()
5490 unsigned ATReg = getATReg(IDLoc); in expandSeqI()
5494 if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc, in expandSeqI()
5498 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSeqI()
5499 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5503 TOut.emitRRI(Opc, DstReg, SrcReg, Imm, IDLoc, STI); in expandSeqI()
5504 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5508 bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSne() argument
5522 warnIfNoMacro(IDLoc); in expandSne()
5525 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSne()
5526 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSne()
5531 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI); in expandSne()
5535 bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSneI() argument
5548 warnIfNoMacro(IDLoc); in expandSneI()
5551 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI); in expandSneI()
5556 Warning(IDLoc, "comparison is always true"); in expandSneI()
5557 if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out, in expandSneI()
5572 TOut.emitRRI(Opc, DstReg, SrcReg, ImmValue, IDLoc, STI); in expandSneI()
5573 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()
5577 unsigned ATReg = getATReg(IDLoc); in expandSneI()
5582 false, IDLoc, Out, STI)) in expandSneI()
5585 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSneI()
5586 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()
5726 bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMXTRAlias() argument
5791 TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc, in expandMXTRAlias()
5796 bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSaaAddr() argument
5802 warnIfNoMacro(IDLoc); in expandSaaAddr()
5813 TOut.emitRR(Opcode, RtReg, BaseReg, IDLoc, STI); in expandSaaAddr()
5818 unsigned ATReg = getATReg(IDLoc); in expandSaaAddr()
5822 if (expandLoadAddress(ATReg, BaseReg, BaseOp, !isGP64bit(), IDLoc, Out, STI)) in expandSaaAddr()
5825 TOut.emitRR(Opcode, RtReg, ATReg, IDLoc, STI); in expandSaaAddr()
5995 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, in MatchAndEmitInstruction() argument
6006 if (processInstruction(Inst, IDLoc, Out, STI)) in MatchAndEmitInstruction()
6010 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); in MatchAndEmitInstruction()
6013 Error(IDLoc, "operand must match destination register"); in MatchAndEmitInstruction()
6016 SMLoc ErrorLoc = IDLoc; in MatchAndEmitInstruction()
6019 return Error(IDLoc, "too few operands for instruction"); in MatchAndEmitInstruction()
6023 ErrorLoc = IDLoc; in MatchAndEmitInstruction()
6029 return Error(IDLoc, in MatchAndEmitInstruction()
6032 return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs"); in MatchAndEmitInstruction()
6034 return Error(IDLoc, "invalid instruction"); in MatchAndEmitInstruction()
6036 return Error(IDLoc, "source and destination must be different"); in MatchAndEmitInstruction()
6038 return Error(IDLoc, "registers must be different"); in MatchAndEmitInstruction()
6040 return Error(IDLoc, "invalid operand ($zero) for instruction"); in MatchAndEmitInstruction()
6042 return Error(IDLoc, "source and destination must match"); in MatchAndEmitInstruction()
6044 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6047 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'"); in MatchAndEmitInstruction()
6049 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6052 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6055 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6058 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6061 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6064 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6067 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6070 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6073 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6076 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6079 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6084 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6087 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6090 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6093 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6096 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6099 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6102 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6105 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6108 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6111 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6114 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6117 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6120 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6125 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6129 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6132 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6135 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6138 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6142 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6145 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6148 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6151 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6154 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6157 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6160 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6163 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6166 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6169 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6172 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()