Lines Matching refs:SR
172 // sub / add which can clobber SR.
173 let isCodeGenOnly = 1, Defs = [SP, SR], Uses = [SP] in {
182 let isCodeGenOnly = 1, Defs = [SR], Uses = [SP] in {
188 let Uses = [SR] in {
198 let Defs = [SR] in {
268 let Uses = [SR] in
282 Defs = [R11, R12, R13, R14, R15, SR],
449 let Defs = [SR], Uses = uses in {
455 (implicit SR)]>;
459 (implicit SR)]>;
464 (implicit SR)]>;
468 (implicit SR)]>;
484 (implicit SR)]>;
488 (implicit SR)]>;
492 (implicit SR)]>;
496 (implicit SR)]>;
501 (implicit SR)]>;
505 (implicit SR)]>;
509 (implicit SR)]>;
513 (implicit SR)]>;
517 (implicit SR)]>;
521 (implicit SR)]>;
526 (implicit SR)]>;
531 (implicit SR)]>;
544 defm ADDC : Arith<0b0110, "addc", adde, 1, [SR]>;
550 defm SUBC : Arith<0b0111, "subc", sube, 0, [SR]>;
551 defm DADD : Arith<0b1010, "dadd", MSP430dadd, 1, [SR]>;
606 def DINT : InstAlias<"dint", (BIC16rc SR, 8)>;
607 def EINT : InstAlias<"eint", (BIS16rc SR, 8)>;
616 def CLRC : InstAlias<"clrc", (BIC16rc SR, 1)>;
617 def CLRN : InstAlias<"clrn", (BIC16rc SR, 4)>;
618 def CLRZ : InstAlias<"clrz", (BIC16rc SR, 2)>;
619 def SETC : InstAlias<"setc", (BIS16rc SR, 1)>;
620 def SETN : InstAlias<"setn", (BIS16rc SR, 4)>;
621 def SETZ : InstAlias<"setz", (BIS16rc SR, 2)>;
630 let Defs = [SR] in {
635 (implicit SR)]>;
640 (implicit SR)]>;
642 let Uses = [SR] in {
647 (implicit SR)]>;
652 (implicit SR)]>;
653 } // Uses = [SR]
659 (implicit SR)]>;
661 } // Defs = [SR]
677 let Defs = [SR] in {
682 (implicit SR)]>;
687 (implicit SR)]>;
694 let Uses = [SR] in {
699 (implicit SR)]>;
704 (implicit SR)]>;
711 } // Uses = [SR]
718 (implicit SR)]>;
722 } // Defs = [SR]
732 let Defs = [SR] in {
736 [(MSP430cmp GR8:$rd, GR8:$rs), (implicit SR)]>;
740 [(MSP430cmp GR16:$rd, GR16:$rs), (implicit SR)]>;
745 [(MSP430cmp GR8:$rd, cg8imm:$imm), (implicit SR)]>;
749 [(MSP430cmp GR16:$rd, cg16imm:$imm), (implicit SR)]>;
754 [(MSP430cmp GR8:$rd, imm:$imm), (implicit SR)]>;
758 [(MSP430cmp GR16:$rd, imm:$imm), (implicit SR)]>;
764 (implicit SR)]>;
769 (implicit SR)]>;
775 (i8 imm:$imm)), (implicit SR)]>;
780 (i16 imm:$imm)), (implicit SR)]>;
786 (implicit SR)]>;
791 (implicit SR)]>;
807 (implicit SR)]>;
812 (implicit SR)]>;
817 (implicit SR)]>;
821 (implicit SR)]>;
840 (implicit SR)]>;
845 (implicit SR)]>;
851 (implicit SR)]>;
856 (implicit SR)]>;
862 (implicit SR)]>;
867 (implicit SR)]>;
873 (implicit SR)]>;
878 (implicit SR)]>;
894 (implicit SR)]>;
899 (implicit SR)]>;
905 (implicit SR)]>;
910 (implicit SR)]>;
916 (implicit SR)]>;
921 (implicit SR)]>;
929 (implicit SR)]>;
936 (implicit SR)]>;
947 } // Defs = [SR]