Lines Matching refs:MSP430
49 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering()
50 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
56 setStackPointerRegisterToSaveRestore(MSP430::SP); in MSP430TargetLowering()
403 return std::make_pair(0U, &MSP430::GR8RegClass); in getRegForInlineAsmConstraint()
405 return std::make_pair(0U, &MSP430::GR16RegClass); in getRegForInlineAsmConstraint()
460 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 in AnalyzeArguments()
464 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in AnalyzeArguments()
465 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 in AnalyzeArguments()
654 Register VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); in LowerCCCArguments()
784 unsigned R12 = MSP430::R12; in LowerReturn()
856 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT); in LowerCCCCallTo()
1197 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR, in LowerSETCC()
1297 MSP430::R4, VT); in LowerFRAMEADDR()
1429 case MSP430::Shl8: in EmitShiftInstr()
1430 Opc = MSP430::ADD8rr; in EmitShiftInstr()
1431 RC = &MSP430::GR8RegClass; in EmitShiftInstr()
1433 case MSP430::Shl16: in EmitShiftInstr()
1434 Opc = MSP430::ADD16rr; in EmitShiftInstr()
1435 RC = &MSP430::GR16RegClass; in EmitShiftInstr()
1437 case MSP430::Sra8: in EmitShiftInstr()
1438 Opc = MSP430::RRA8r; in EmitShiftInstr()
1439 RC = &MSP430::GR8RegClass; in EmitShiftInstr()
1441 case MSP430::Sra16: in EmitShiftInstr()
1442 Opc = MSP430::RRA16r; in EmitShiftInstr()
1443 RC = &MSP430::GR16RegClass; in EmitShiftInstr()
1445 case MSP430::Srl8: in EmitShiftInstr()
1447 Opc = MSP430::RRC8r; in EmitShiftInstr()
1448 RC = &MSP430::GR8RegClass; in EmitShiftInstr()
1450 case MSP430::Srl16: in EmitShiftInstr()
1452 Opc = MSP430::RRC16r; in EmitShiftInstr()
1453 RC = &MSP430::GR16RegClass; in EmitShiftInstr()
1455 case MSP430::Rrcl8: in EmitShiftInstr()
1456 case MSP430::Rrcl16: { in EmitShiftInstr()
1457 BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR) in EmitShiftInstr()
1458 .addReg(MSP430::SR).addImm(1); in EmitShiftInstr()
1461 unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16 in EmitShiftInstr()
1462 ? MSP430::RRC16r : MSP430::RRC8r; in EmitShiftInstr()
1492 Register ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass); in EmitShiftInstr()
1493 Register ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass); in EmitShiftInstr()
1503 BuildMI(BB, dl, TII.get(MSP430::CMP8ri)) in EmitShiftInstr()
1505 BuildMI(BB, dl, TII.get(MSP430::JCC)) in EmitShiftInstr()
1514 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) in EmitShiftInstr()
1517 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg) in EmitShiftInstr()
1521 BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR) in EmitShiftInstr()
1522 .addReg(MSP430::SR).addImm(1); in EmitShiftInstr()
1523 if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr) in EmitShiftInstr()
1530 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2) in EmitShiftInstr()
1532 BuildMI(LoopBB, dl, TII.get(MSP430::JCC)) in EmitShiftInstr()
1538 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg) in EmitShiftInstr()
1551 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 || in EmitInstrWithCustomInserter()
1552 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 || in EmitInstrWithCustomInserter()
1553 Opc == MSP430::Srl8 || Opc == MSP430::Srl16 || in EmitInstrWithCustomInserter()
1554 Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16) in EmitInstrWithCustomInserter()
1560 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) && in EmitInstrWithCustomInserter()
1591 BuildMI(BB, dl, TII.get(MSP430::JCC)) in EmitInstrWithCustomInserter()
1607 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg()) in EmitInstrWithCustomInserter()