Lines Matching +full:invert +full:- +full:ext
1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
37 #define DEBUG_TYPE "msp430-lower"
40 "msp430-no-legal-immediate", cl::Hidden,
60 // We have post-incremented loads / stores. in MSP430TargetLowering()
152 // EABI Libcalls - EABI Section 6.2 in MSP430TargetLowering()
158 // Floating point conversions - EABI Table 6 in MSP430TargetLowering()
198 // Floating point comparisons - EABI Table 7 in MSP430TargetLowering()
212 // Floating point arithmetic - EABI Table 8 in MSP430TargetLowering()
225 // Universal Integer Operations - EABI Table 9 in MSP430TargetLowering()
239 // Bitwise Operations - EABI Table 10 in MSP430TargetLowering()
259 // Integer Multiply - EABI Table 9 in MSP430TargetLowering()
274 // Integer Multiply - EABI Table 9 in MSP430TargetLowering()
289 // Integer Multiply - EABI Table 9 in MSP430TargetLowering()
304 // Integer Multiply - EABI Table 9 in MSP430TargetLowering()
368 // tests/codegen/msp430/shift-amount-threshold-b.ll
371 return Immed >= -32 && Immed < 32; in isLegalICmpImmediate()
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 /// getConstraintType - Given a constraint letter, return the type of
412 //===----------------------------------------------------------------------===//
414 //===----------------------------------------------------------------------===//
525 "Builtin calling convention requires 64-bit arguments"); in AnalyzeArguments()
529 // Special case for 32-bit register split, see EABI section 3.3.3 in AnalyzeArguments()
532 RegsLeft -= 1; in AnalyzeArguments()
540 RegsLeft--; in AnalyzeArguments()
615 /// LowerCCCArguments - transform physical registers into virtual registers and
636 FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true)); in LowerCCCArguments()
658 // If this is an 8-bit value, it is really passed promoted to 16 in LowerCCCArguments()
659 // bits. Insert an assert[sz]ext to capture this, then truncate to the in LowerCCCArguments()
709 Register Reg = FuncInfo->getSRetReturnReg(); in LowerCCCArguments()
713 FuncInfo->setSRetReturnReg(Reg); in LowerCCCArguments()
743 // CCValAssign - represent the assignment of the return value to a location in LowerReturn()
750 // CCState - Info about the registers and stack slot. in LowerReturn()
776 Register Reg = FuncInfo->getSRetReturnReg(); in LowerReturn()
803 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
886 // Build a sequence of copy-to-reg nodes chained together with token chain and in LowerCCCCallTo()
898 // Likewise ExternalSymbol -> TargetExternalSymbol. in LowerCCCCallTo()
900 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16); in LowerCCCCallTo()
902 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16); in LowerCCCCallTo()
932 /// LowerCallResult - Lower the result values of a call into the
965 // Expand non-constant shifts to loops: in LowerShifts()
966 if (!isa<ConstantSDNode>(N->getOperand(1))) in LowerShifts()
969 uint64_t ShiftAmount = N->getConstantOperandVal(1); in LowerShifts()
972 SDValue Victim = N->getOperand(0); in LowerShifts()
994 ShiftAmount -= 8; in LowerShifts()
1001 ShiftAmount -= 1; in LowerShifts()
1004 while (ShiftAmount--) in LowerShifts()
1013 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); in LowerGlobalAddress()
1014 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); in LowerGlobalAddress()
1025 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); in LowerExternalSymbol()
1035 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); in LowerBlockAddress()
1073 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); in EmitCMP()
1087 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); in EmitCMP()
1101 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); in EmitCMP()
1115 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); in EmitCMP()
1130 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
1151 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so in LowerSETCC()
1157 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
1165 bool Invert = false; in LowerSETCC() local
1168 switch (TargetCC->getAsZExtVal()) { in LowerSETCC()
1177 Invert = true; in LowerSETCC()
1185 Invert = true; in LowerSETCC()
1203 if (Invert) in LowerSETCC()
1219 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
1247 int ReturnAddrIndex = FuncInfo->getRAIndex(); in getReturnAddressFrameIndex()
1253 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize, in getReturnAddressFrameIndex()
1255 FuncInfo->setRAIndex(ReturnAddrIndex); in getReturnAddressFrameIndex()
1298 while (Depth--) in LowerFRAMEADDR()
1314 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); in LowerVASTART()
1315 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); in LowerVASTART()
1326 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); in LowerJumpTable()
1330 /// getPostIndexedAddressParts - returns true by value, base pointer and
1332 /// combined with a load / store to form a post-indexed load / store.
1340 if (LD->getExtensionType() != ISD::NON_EXTLOAD) in getPostIndexedAddressParts()
1343 EVT VT = LD->getMemoryVT(); in getPostIndexedAddressParts()
1347 if (Op->getOpcode() != ISD::ADD) in getPostIndexedAddressParts()
1350 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { in getPostIndexedAddressParts()
1351 uint64_t RHSC = RHS->getZExtValue(); in getPostIndexedAddressParts()
1356 Base = Op->getOperand(0); in getPostIndexedAddressParts()
1388 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) in isTruncateFree()
1391 return (Ty1->getPrimitiveSizeInBits().getFixedValue() > in isTruncateFree()
1392 Ty2->getPrimitiveSizeInBits().getFixedValue()); in isTruncateFree()
1403 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. in isZExtFree()
1404 return false && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16); in isZExtFree()
1408 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. in isZExtFree()
1412 //===----------------------------------------------------------------------===//
1414 //===----------------------------------------------------------------------===//
1419 MachineFunction *F = BB->getParent(); in EmitShiftInstr()
1420 MachineRegisterInfo &RI = F->getRegInfo(); in EmitShiftInstr()
1422 const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo(); in EmitShiftInstr()
1470 const BasicBlock *LLVM_BB = BB->getBasicBlock(); in EmitShiftInstr()
1471 MachineFunction::iterator I = ++BB->getIterator(); in EmitShiftInstr()
1474 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); in EmitShiftInstr()
1475 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); in EmitShiftInstr()
1477 F->insert(I, LoopBB); in EmitShiftInstr()
1478 F->insert(I, RemBB); in EmitShiftInstr()
1480 // Update machine-CFG edges by transferring all successors of the current in EmitShiftInstr()
1482 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), in EmitShiftInstr()
1483 BB->end()); in EmitShiftInstr()
1484 RemBB->transferSuccessorsAndUpdatePHIs(BB); in EmitShiftInstr()
1487 BB->addSuccessor(LoopBB); in EmitShiftInstr()
1488 BB->addSuccessor(RemBB); in EmitShiftInstr()
1489 LoopBB->addSuccessor(RemBB); in EmitShiftInstr()
1490 LoopBB->addSuccessor(LoopBB); in EmitShiftInstr()
1513 // ShiftAmt2 = ShiftAmt - 1; in EmitShiftInstr()
1538 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg) in EmitShiftInstr()
1557 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); in EmitInstrWithCustomInserter()
1564 // control-flow pattern. The incoming instruction knows the destination vreg in EmitInstrWithCustomInserter()
1567 const BasicBlock *LLVM_BB = BB->getBasicBlock(); in EmitInstrWithCustomInserter()
1568 MachineFunction::iterator I = ++BB->getIterator(); in EmitInstrWithCustomInserter()
1575 // fallthrough --> copy0MBB in EmitInstrWithCustomInserter()
1577 MachineFunction *F = BB->getParent(); in EmitInstrWithCustomInserter()
1578 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); in EmitInstrWithCustomInserter()
1579 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); in EmitInstrWithCustomInserter()
1580 F->insert(I, copy0MBB); in EmitInstrWithCustomInserter()
1581 F->insert(I, copy1MBB); in EmitInstrWithCustomInserter()
1582 // Update machine-CFG edges by transferring all successors of the current in EmitInstrWithCustomInserter()
1584 copy1MBB->splice(copy1MBB->begin(), BB, in EmitInstrWithCustomInserter()
1585 std::next(MachineBasicBlock::iterator(MI)), BB->end()); in EmitInstrWithCustomInserter()
1586 copy1MBB->transferSuccessorsAndUpdatePHIs(BB); in EmitInstrWithCustomInserter()
1588 BB->addSuccessor(copy0MBB); in EmitInstrWithCustomInserter()
1589 BB->addSuccessor(copy1MBB); in EmitInstrWithCustomInserter()
1600 // Update machine-CFG edges in EmitInstrWithCustomInserter()
1601 BB->addSuccessor(copy1MBB); in EmitInstrWithCustomInserter()
1607 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg()) in EmitInstrWithCustomInserter()