Lines Matching refs:M68k
44 : M68kGenInstrInfo(M68k::ADJCALLSTACKDOWN, M68k::ADJCALLSTACKUP, 0, in M68kInstrInfo()
45 M68k::RET), in M68kInstrInfo()
48 static M68k::CondCode getCondFromBranchOpc(unsigned BrOpc) { in getCondFromBranchOpc()
51 return M68k::COND_INVALID; in getCondFromBranchOpc()
52 case M68k::Beq8: in getCondFromBranchOpc()
53 return M68k::COND_EQ; in getCondFromBranchOpc()
54 case M68k::Bne8: in getCondFromBranchOpc()
55 return M68k::COND_NE; in getCondFromBranchOpc()
56 case M68k::Blt8: in getCondFromBranchOpc()
57 return M68k::COND_LT; in getCondFromBranchOpc()
58 case M68k::Ble8: in getCondFromBranchOpc()
59 return M68k::COND_LE; in getCondFromBranchOpc()
60 case M68k::Bgt8: in getCondFromBranchOpc()
61 return M68k::COND_GT; in getCondFromBranchOpc()
62 case M68k::Bge8: in getCondFromBranchOpc()
63 return M68k::COND_GE; in getCondFromBranchOpc()
64 case M68k::Bcs8: in getCondFromBranchOpc()
65 return M68k::COND_CS; in getCondFromBranchOpc()
66 case M68k::Bls8: in getCondFromBranchOpc()
67 return M68k::COND_LS; in getCondFromBranchOpc()
68 case M68k::Bhi8: in getCondFromBranchOpc()
69 return M68k::COND_HI; in getCondFromBranchOpc()
70 case M68k::Bcc8: in getCondFromBranchOpc()
71 return M68k::COND_CC; in getCondFromBranchOpc()
72 case M68k::Bmi8: in getCondFromBranchOpc()
73 return M68k::COND_MI; in getCondFromBranchOpc()
74 case M68k::Bpl8: in getCondFromBranchOpc()
75 return M68k::COND_PL; in getCondFromBranchOpc()
76 case M68k::Bvs8: in getCondFromBranchOpc()
77 return M68k::COND_VS; in getCondFromBranchOpc()
78 case M68k::Bvc8: in getCondFromBranchOpc()
79 return M68k::COND_VC; in getCondFromBranchOpc()
120 if (Opcode == M68k::BRA8 || Opcode == M68k::BRA16) { in AnalyzeBranchImpl()
148 auto BranchCode = M68k::GetCondFromBranchOpc(Opcode); in AnalyzeBranchImpl()
151 if (BranchCode == M68k::COND_INVALID) in AnalyzeBranchImpl()
235 auto OldBranchCode = static_cast<M68k::CondCode>(Cond[0].getImm()); in AnalyzeBranchImpl()
268 if (I->getOpcode() != M68k::BRA8 && in removeBranch()
269 getCondFromBranchOpc(I->getOpcode()) == M68k::COND_INVALID) in removeBranch()
292 BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(TBB); in insertBranch()
301 M68k::CondCode CC = (M68k::CondCode)Cond[0].getImm(); in insertBranch()
307 BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(FBB); in insertBranch()
320 R = RI.getSubReg(Reg, M68k::MxSubRegIndex16Lo); in AddSExt()
323 BuildMI(MBB, I, DL, get(M68k::EXT16), R).addReg(R); in AddSExt()
327 BuildMI(MBB, I, DL, get(M68k::EXT32), Reg).addReg(Reg); in AddSExt()
341 And = M68k::AND16di; in AddZExt()
343 And = M68k::AND32di; in AddZExt()
356 const auto *DR32 = RI.getRegClass(M68k::DR32RegClassID); in ExpandMOVI()
357 const auto *AR32 = RI.getRegClass(M68k::AR32RegClassID); in ExpandMOVI()
358 const auto *AR16 = RI.getRegClass(M68k::AR16RegClassID); in ExpandMOVI()
373 MIB->setDesc(get(M68k::MOVQ)); in ExpandMOVI()
377 MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri)); in ExpandMOVI()
385 unsigned Move = MVTDst == MVT::i16 ? M68k::MOV16rr : M68k::MOV32rr; in ExpandMOVX_RR()
429 Move = M68k::MOV16rr; in ExpandMOVSZX_RR()
431 Move = M68k::MOV32rr; in ExpandMOVSZX_RR()
485 RI.getSubReg(Dst, MVTSrc == MVT::i8 ? M68k::MxSubRegIndex8Lo in ExpandMOVSZX_RM()
486 : M68k::MxSubRegIndex16Lo); in ExpandMOVSZX_RM()
529 MIB->setDesc(get(M68k::MOV16cd)); in ExpandCCR()
532 MIB->setDesc(get(M68k::MOV16dc)); in ExpandCCR()
537 Opd.getReg(), M68k::MxSubRegIndex8Lo, &M68k::DR16RegClass)); in ExpandCCR()
545 auto XR32 = RI.getRegClass(M68k::XR32RegClassID); in ExpandMOVEM()
614 case M68k::PUSH8d: in expandPostRAPseudo()
615 return ExpandPUSH_POP(MIB, get(M68k::MOV8ed), true); in expandPostRAPseudo()
616 case M68k::PUSH16d: in expandPostRAPseudo()
617 return ExpandPUSH_POP(MIB, get(M68k::MOV16er), true); in expandPostRAPseudo()
618 case M68k::PUSH32r: in expandPostRAPseudo()
619 return ExpandPUSH_POP(MIB, get(M68k::MOV32er), true); in expandPostRAPseudo()
621 case M68k::POP8d: in expandPostRAPseudo()
622 return ExpandPUSH_POP(MIB, get(M68k::MOV8do), false); in expandPostRAPseudo()
623 case M68k::POP16d: in expandPostRAPseudo()
624 return ExpandPUSH_POP(MIB, get(M68k::MOV16ro), false); in expandPostRAPseudo()
625 case M68k::POP32r: in expandPostRAPseudo()
626 return ExpandPUSH_POP(MIB, get(M68k::MOV32ro), false); in expandPostRAPseudo()
628 case M68k::SETCS_C8d: in expandPostRAPseudo()
629 return Expand2AddrUndef(MIB, get(M68k::SUBX8dd)); in expandPostRAPseudo()
630 case M68k::SETCS_C16d: in expandPostRAPseudo()
631 return Expand2AddrUndef(MIB, get(M68k::SUBX16dd)); in expandPostRAPseudo()
632 case M68k::SETCS_C32d: in expandPostRAPseudo()
633 return Expand2AddrUndef(MIB, get(M68k::SUBX32dd)); in expandPostRAPseudo()
670 if (M68k::XR32RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
671 Opc = M68k::MOV32rr; in copyPhysReg()
672 else if (M68k::XR16RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
673 Opc = M68k::MOV16rr; in copyPhysReg()
674 else if (M68k::DR8RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
675 Opc = M68k::MOV8dd; in copyPhysReg()
690 if (M68k::DR8RegClass.contains(SrcReg)) { in copyPhysReg()
691 if (M68k::XR16RegClass.contains(DstReg)) in copyPhysReg()
692 Opc = M68k::MOVXd16d8; in copyPhysReg()
693 else if (M68k::XR32RegClass.contains(DstReg)) in copyPhysReg()
694 Opc = M68k::MOVXd32d8; in copyPhysReg()
695 } else if (M68k::XR16RegClass.contains(SrcReg) && in copyPhysReg()
696 M68k::XR32RegClass.contains(DstReg)) in copyPhysReg()
697 Opc = M68k::MOVXd32d16; in copyPhysReg()
705 bool FromCCR = SrcReg == M68k::CCR; in copyPhysReg()
706 bool FromSR = SrcReg == M68k::SR; in copyPhysReg()
707 bool ToCCR = DstReg == M68k::CCR; in copyPhysReg()
708 bool ToSR = DstReg == M68k::SR; in copyPhysReg()
711 assert(M68k::DR8RegClass.contains(DstReg) && in copyPhysReg()
713 Opc = M68k::MOV8dc; in copyPhysReg()
715 assert(M68k::DR8RegClass.contains(SrcReg) && in copyPhysReg()
717 Opc = M68k::MOV8cd; in copyPhysReg()
740 if (M68k::DR8RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
741 return load ? M68k::MOV8dp : M68k::MOV8pd; in getLoadStoreRegOpcode()
742 if (M68k::CCRCRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
743 return load ? M68k::MOV16cp : M68k::MOV16pc; in getLoadStoreRegOpcode()
747 assert(M68k::XR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
748 return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P; in getLoadStoreRegOpcode()
750 assert(M68k::XR32RegClass.hasSubClassEq(RC) && "Unknown 4-byte regclass"); in getLoadStoreRegOpcode()
751 return load ? M68k::MOVM32mp_P : M68k::MOVM32pm_P; in getLoadStoreRegOpcode()
790 M68k::addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIndex) in storeRegToStackSlot()
807 M68k::addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DstReg), FrameIndex); in loadRegFromStackSlot()
831 GlobalBaseReg = RegInfo.createVirtualRegister(&M68k::AR32_NOSPRegClass); in getGlobalBaseReg()
887 BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), GlobalBaseReg) in runOnMachineFunction()