Lines Matching +full:rx +full:- +full:eq
1 //===-- M68kInstrArithmetic.td - Integer Arith Instrs ------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
23 /// [ ] - was not touched at all
24 /// [!] - requires extarnal stuff implemented
25 /// [~] - functional implementation
26 /// [X] - complete implementation
28 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
32 //===----------------------------------------------------------------------===//
52 //===----------------------------------------------------------------------===//
54 //===----------------------------------------------------------------------===//
60 /// ----------------------------------------------------
62 /// ----------------------------------------------------
65 /// ----------------------------------------------------
67 // $reg, $ccr <- $reg op $reg
77 !eq(SRC_TYPE.RLet, "r") : (descend 0b00, (operand "$opd", 4)),
78 !eq(SRC_TYPE.RLet, "d") : (descend 0b000, (operand "$opd", 3))
116 /// ---------------------------------------------------
118 /// ---------------------------------------------------
121 /// ---------------------------------------------------
122 /// 16-BIT WORD DATA | 8-BIT BYTE DATA
123 /// ---------------------------------------------------
124 /// 32-BIT LONG DATA
125 /// ---------------------------------------------------
126 /// NOTE It is used to store an immediate to memory, imm-to-reg are handled with
129 // $reg <- $reg op $imm
306 //===----------------------------------------------------------------------===//
308 //===----------------------------------------------------------------------===//
316 // for global values that are allocated in thread-local storage, i.e.:
326 /// ------------------------------------------------------
328 /// ------------------------------------------------------
329 /// x x x x | REG Rx | 1 | SIZE | 0 0 | M | REG Ry
330 /// ------------------------------------------------------
331 /// Rx - destination
332 /// Ry - source
333 /// M - address mode switch
335 // $reg, ccr <- $reg op $reg op ccr
345 !cond(!eq(TYPE.Size, 8): 0b00,
346 !eq(TYPE.Size, 16): 0b01,
347 !eq(TYPE.Size, 32): 0b10),
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
393 //===----------------------------------------------------------------------===//
395 //===----------------------------------------------------------------------===//
528 //===----------------------------------------------------------------------===//
530 //===----------------------------------------------------------------------===//
532 /// ---------------------------------------------------
534 /// ---------------------------------------------------
536 /// ---------------------------------------------------
545 // byte -> word
546 !and(!eq(FROM.Size, 8), !eq(TO.Size, 16)): 0b010,
547 // word -> long
548 !and(!eq(FROM.Size, 16), !eq(TO.Size, 32)): 0b011,
549 // byte -> long
550 !and(!eq(FROM.Size, 8), !eq(TO.Size, 32)): 0b111
567 //===----------------------------------------------------------------------===//
569 //===----------------------------------------------------------------------===//
572 /// ----------------------------------------------------
574 /// ----------------------------------------------------
577 /// ----------------------------------------------------
580 // $dreg <- $dreg op $dreg
592 // $dreg <- $dreg op $dreg
609 // $reg <- $reg op $imm
639 // This is used to cast immediates to 16-bits for operations which don't
642 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
771 //===----------------------------------------------------------------------===//
773 //===----------------------------------------------------------------------===//
775 /// ------------+------------+------+---------+---------
777 /// ------------+------------+------+-------------------
780 /// ------------+------------+------+---------+---------
844 //===----------------------------------------------------------------------===//
845 // no-CCR Patterns
846 //===----------------------------------------------------------------------===//
850 /// MxAdd and MxSub instructions that produce CCR and then pattern-map add and addc
1003 //===----------------------------------------------------------------------===//
1005 //===----------------------------------------------------------------------===//
1011 let Uses = !if(!eq(rounding, ""), [FPC], []);
1013 let Predicates = !if(!eq(rounding, ""), [AtLeastM68881], [AtLeastM68040]);
1018 bits<7> Mode = !cond(!eq(rounding, "s"): single,
1019 !eq(rounding, "d"): double,
1020 !eq(rounding, ""): extended);
1023 //===----------------------------------------------------------------------===//
1025 //===----------------------------------------------------------------------===//
1065 //===----------------------------------------------------------------------===//
1067 //===----------------------------------------------------------------------===//