Lines Matching refs:rj
14 // rj/rk/sj - source register operand.
26 // <opcode | rj>
28 : LAInst<(outs), (ins GPR:$rj),
29 deriveInsnMnemonic<NAME>.ret, "$rj"> {
30 bits<5> rj;
33 let Inst{9-5} = rj;
37 // <opcode | I3 | rj>
39 : LAInst<(outs), (ins GPR:$rj, uimm3:$imm3),
40 deriveInsnMnemonic<NAME>.ret, "$rj, $imm3"> {
42 bits<5> rj;
46 let Inst{9-5} = rj;
50 // <opcode | I4 | rj>
52 : LAInst<(outs), (ins GPR:$rj, uimm4:$imm4),
53 deriveInsnMnemonic<NAME>.ret, "$rj, $imm4"> {
55 bits<5> rj;
59 let Inst{9-5} = rj;
76 // <opcode | I5 | rj>
78 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5),
79 deriveInsnMnemonic<NAME>.ret, "$rj, $imm5"> {
81 bits<5> rj;
85 let Inst{9-5} = rj;
91 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5, uimm4:$imm4),
92 deriveInsnMnemonic<NAME>.ret, "$rj, $imm5, $imm4"> {
94 bits<5> rj;
99 let Inst{9-5} = rj;
119 // <opcode | I6 | rj>
121 : LAInst<(outs), (ins GPR:$rj, uimm6:$imm6),
122 deriveInsnMnemonic<NAME>.ret, "$rj, $imm6"> {
124 bits<5> rj;
128 let Inst{9-5} = rj;
145 // <opcode | rk | rj>
147 : LAInst<(outs), (ins GPR:$rj, GPR:$rk),
148 deriveInsnMnemonic<NAME>.ret, "$rj, $rk"> {
150 bits<5> rj;
154 let Inst{9-5} = rj;
158 // <opcode | rk | rj | imm4>
160 : LAInst<(outs), (ins GPR:$rj, GPR:$rk, uimm4:$imm4),
161 deriveInsnMnemonic<NAME>.ret, "$rj, $rk, $imm4"> {
164 bits<5> rj;
168 let Inst{9-5} = rj;
173 // <opcode | I3 | rj | rd>
175 : LAInst<(outs GPR:$rd), (ins GPR:$rj, uimm3:$imm3),
176 deriveInsnMnemonic<NAME>.ret, "$rd, $rj, $imm3"> {
178 bits<5> rj;
183 let Inst{9-5} = rj;
188 // <opcode | I4 | rj | rd>
190 : LAInst<(outs GPR:$rd), (ins GPR:$rj, uimm4:$imm4),
191 deriveInsnMnemonic<NAME>.ret, "$rd, $rj, $imm4"> {
193 bits<5> rj;
198 let Inst{9-5} = rj;
202 // <opcode | rj | sd>
204 : LAInst<(outs SCR:$sd), (ins GPR:$rj), deriveInsnMnemonic<NAME>.ret,
205 "$sd, $rj"> {
206 bits<5> rj;
210 let Inst{9-5} = rj;
231 bits<5> rj;