Lines Matching +full:0 +full:x38100000
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
20 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
24 def SDT_LoongArchCall : SDTypeProfile<0, -1, [SDTCisVT<0, GRLenVT>]>;
26 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64>
30 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>,
35 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisSameAs<2, 3>
39 def SDT_LoongArchVI : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>;
41 def SDT_LoongArchCsrrd : SDTypeProfile<1, 1, [SDTCisInt<0>,
43 def SDT_LoongArchCsrwr : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 def SDT_LoongArchCsrxchg : SDTypeProfile<1, 3, [SDTCisInt<0>,
46 SDTCisSameAs<0, 1>,
47 SDTCisSameAs<0, 2>,
49 def SDT_LoongArchIocsrwr : SDTypeProfile<0, 2, [SDTCisInt<0>,
50 SDTCisSameAs<0, 1>]>;
51 def SDT_LoongArchMovgr2fcsr : SDTypeProfile<0, 2, [SDTCisVT<0, GRLenVT>,
52 SDTCisSameAs<0, 1>]>;
53 def SDT_LoongArchMovfcsr2gr : SDTypeProfile<1, 1, [SDTCisVT<0, GRLenVT>,
54 SDTCisSameAs<0, 1>]>;
161 unsigned Mask = 0;
204 // A parse method for "$r*" or "$r*, 0", where the 0 is be silently ignored.
485 N->getValueType(0));
496 N->getValueType(0));
502 SDLoc(N), N->getValueType(0));
508 N->getValueType(0));
516 SDLoc(N), N->getValueType(0));
540 int64_t Imm = N->getSExtValue() < 0 ? -2048 : 2047;
542 N->getValueType(0));
545 // Return imm - (imm < 0 ? -2048 : 2047).
548 int64_t Adj = Imm < 0 ? -2048 : 2047;
550 N->getValueType(0));
568 N->getValueType(0));
582 N->getValueType(0));
591 // andi can be used instead if Imm <= 0xfff.
592 if (Imm <= 0xfff)
595 return N->getValueType(0).getSizeInBits() == 32
603 N->getValueType(0).getSizeInBits() == 32
607 N->getValueType(0));
613 N->getValueType(0).getSizeInBits() == 32
616 return CurDAG->getTargetConstant(MaskIdx, SDLoc(N), N->getValueType(0));
633 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
659 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
661 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
665 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
669 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
688 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
690 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
699 } // hasSideEffects = 0, mayLoad = 1, mayStore = 0
701 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
711 } // hasSideEffects = 0, mayLoad = 0, mayStore = 1
713 let hasSideEffects = 0, mayLoad = 1, mayStore = 1, Constraints = "@earlyclobber $rd" in
718 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
726 let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rd = $dst" in {
750 def ADD_W : ALU_3R<0x00100000>;
751 def SUB_W : ALU_3R<0x00110000>;
752 def ADDI_W : ALU_2RI12<0x02800000, simm12_addlike>;
753 def ALSL_W : ALU_3RI2<0x00040000, uimm2_plus1>;
755 def LU12I_W : ALU_1RI20<0x14000000, simm20_lu12iw>;
757 def SLT : ALU_3R<0x00120000>;
758 def SLTU : ALU_3R<0x00128000>;
759 def SLTI : ALU_2RI12<0x02000000, simm12>;
760 def SLTUI : ALU_2RI12<0x02400000, simm12>;
761 def PCADDI : ALU_1RI20<0x18000000, simm20_pcaddi>;
762 def PCADDU12I : ALU_1RI20<0x1c000000, simm20>;
763 def PCALAU12I : ALU_1RI20<0x1a000000, simm20_pcalau12i>;
764 def AND : ALU_3R<0x00148000>;
765 def OR : ALU_3R<0x00150000>;
766 def NOR : ALU_3R<0x00140000>;
767 def XOR : ALU_3R<0x00158000>;
768 def ANDN : ALU_3R<0x00168000>;
769 def ORN : ALU_3R<0x00160000>;
770 def ANDI : ALU_2RI12<0x03400000, uimm12>;
773 def ORI : ALU_2RI12<0x03800000, uimm12_ori>;
774 def XORI : ALU_2RI12<0x03c00000, uimm12>;
776 def MUL_W : ALU_3R<0x001c0000>;
777 def MULH_W : ALU_3R<0x001c8000>;
778 def MULH_WU : ALU_3R<0x001d0000>;
780 def DIV_W : ALU_3R<0x00200000>;
781 def MOD_W : ALU_3R<0x00208000>;
782 def DIV_WU : ALU_3R<0x00210000>;
783 def MOD_WU : ALU_3R<0x00218000>;
787 def SLL_W : ALU_3R<0x00170000>;
788 def SRL_W : ALU_3R<0x00178000>;
789 def SRA_W : ALU_3R<0x00180000>;
790 def ROTR_W : ALU_3R<0x001b0000>;
792 def SLLI_W : ALU_2RI5<0x00408000, uimm5>;
793 def SRLI_W : ALU_2RI5<0x00448000, uimm5>;
794 def SRAI_W : ALU_2RI5<0x00488000, uimm5>;
795 def ROTRI_W : ALU_2RI5<0x004c8000, uimm5>;
798 def EXT_W_B : ALU_2R<0x00005c00>;
799 def EXT_W_H : ALU_2R<0x00005800>;
800 def CLO_W : ALU_2R<0x00001000>;
801 def CLZ_W : ALU_2R<0x00001400>;
802 def CTO_W : ALU_2R<0x00001800>;
803 def CTZ_W : ALU_2R<0x00001c00>;
804 def BYTEPICK_W : ALU_3RI2<0x00080000, uimm2>;
805 def REVB_2H : ALU_2R<0x00003000>;
806 def BITREV_4B : ALU_2R<0x00004800>;
807 def BITREV_W : ALU_2R<0x00005000>;
809 def BSTRINS_W : FmtBSTR_W<0x00600000, (outs GPR:$dst),
813 def BSTRPICK_W : FmtBSTR_W<0x00608000, (outs GPR:$rd),
816 def MASKEQZ : ALU_3R<0x00130000>;
817 def MASKNEZ : ALU_3R<0x00138000>;
820 def BEQ : BrCC_2RI16<0x58000000>;
821 def BNE : BrCC_2RI16<0x5c000000>;
822 def BLT : BrCC_2RI16<0x60000000>;
823 def BGE : BrCC_2RI16<0x64000000>;
824 def BLTU : BrCC_2RI16<0x68000000>;
825 def BGEU : BrCC_2RI16<0x6c000000>;
826 def BEQZ : BrCCZ_1RI21<0x40000000>;
827 def BNEZ : BrCCZ_1RI21<0x44000000>;
828 def B : Br_I26<0x50000000>;
830 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1, Defs=[R1] in
831 def BL : FmtI26<0x54000000, (outs), (ins simm26_symbol:$imm26), "$imm26">;
832 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
833 def JIRL : Fmt2RI16<0x4c000000, (outs GPR:$rd),
837 def LD_B : LOAD_2RI12<0x28000000>;
838 def LD_H : LOAD_2RI12<0x28400000>;
839 def LD_W : LOAD_2RI12<0x28800000>;
840 def LD_BU : LOAD_2RI12<0x2a000000>;
841 def LD_HU : LOAD_2RI12<0x2a400000>;
842 def ST_B : STORE_2RI12<0x29000000>;
843 def ST_H : STORE_2RI12<0x29400000>;
844 def ST_W : STORE_2RI12<0x29800000>;
845 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
850 def LL_W : LLBase<0x20000000>;
851 def SC_W : SCBase<0x21000000>;
852 def LLACQ_W : LLBase_ACQ<0x38578000>;
853 def SCREL_W : SCBase_REL<0x38578400>;
856 def DBAR : MISC_I15<0x38720000>;
857 def IBAR : MISC_I15<0x38728000>;
860 def SYSCALL : MISC_I15<0x002b0000>;
861 def BREAK : MISC_I15<0x002a0000>;
862 def RDTIMEL_W : RDTIME_2R<0x00006000>;
863 def RDTIMEH_W : RDTIME_2R<0x00006400>;
864 def CPUCFG : ALU_2R<0x00006c00>;
875 def ADD_D : ALU_3R<0x00108000>;
876 def SUB_D : ALU_3R<0x00118000>;
881 def ADDI_D : ALU_2RI12<0x02c00000, simm12_addlike>;
883 def ADDU16I_D : ALU_2RI16<0x10000000, simm16>;
884 def ALSL_WU : ALU_3RI2<0x00060000, uimm2_plus1>;
885 def ALSL_D : ALU_3RI2<0x002c0000, uimm2_plus1>;
887 let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
889 def LU32I_D : Fmt1RI20<0x16000000, (outs GPR:$dst),
894 def LU52I_D : ALU_2RI12<0x03000000, simm12_lu52id>;
896 def PCADDU18I : ALU_1RI20<0x1e000000, simm20_pcaddu18i>;
897 def MUL_D : ALU_3R<0x001d8000>;
898 def MULH_D : ALU_3R<0x001e0000>;
899 def MULH_DU : ALU_3R<0x001e8000>;
900 def MULW_D_W : ALU_3R<0x001f0000>;
901 def MULW_D_WU : ALU_3R<0x001f8000>;
903 def DIV_D : ALU_3R<0x00220000>;
904 def MOD_D : ALU_3R<0x00228000>;
905 def DIV_DU : ALU_3R<0x00230000>;
906 def MOD_DU : ALU_3R<0x00238000>;
910 def SLL_D : ALU_3R<0x00188000>;
911 def SRL_D : ALU_3R<0x00190000>;
912 def SRA_D : ALU_3R<0x00198000>;
913 def ROTR_D : ALU_3R<0x001b8000>;
914 def SLLI_D : ALU_2RI6<0x00410000, uimm6>;
915 def SRLI_D : ALU_2RI6<0x00450000, uimm6>;
916 def SRAI_D : ALU_2RI6<0x00490000, uimm6>;
917 def ROTRI_D : ALU_2RI6<0x004d0000, uimm6>;
920 def CLO_D : ALU_2R<0x00002000>;
921 def CLZ_D : ALU_2R<0x00002400>;
922 def CTO_D : ALU_2R<0x00002800>;
923 def CTZ_D : ALU_2R<0x00002c00>;
924 def BYTEPICK_D : ALU_3RI3<0x000c0000, uimm3>;
925 def REVB_4H : ALU_2R<0x00003400>;
926 def REVB_2W : ALU_2R<0x00003800>;
927 def REVB_D : ALU_2R<0x00003c00>;
928 def REVH_2W : ALU_2R<0x00004000>;
929 def REVH_D : ALU_2R<0x00004400>;
930 def BITREV_8B : ALU_2R<0x00004c00>;
931 def BITREV_D : ALU_2R<0x00005400>;
933 def BSTRINS_D : FmtBSTR_D<0x00800000, (outs GPR:$dst),
937 def BSTRPICK_D : FmtBSTR_D<0x00c00000, (outs GPR:$rd),
942 def LD_WU : LOAD_2RI12<0x2a800000>;
943 def LD_D : LOAD_2RI12<0x28c00000>;
944 def ST_D : STORE_2RI12<0x29c00000>;
945 def LDX_B : LOAD_3R<0x38000000>;
946 def LDX_H : LOAD_3R<0x38040000>;
947 def LDX_W : LOAD_3R<0x38080000>;
948 def LDX_D : LOAD_3R<0x380c0000>;
949 def LDX_BU : LOAD_3R<0x38200000>;
950 def LDX_HU : LOAD_3R<0x38240000>;
951 def LDX_WU : LOAD_3R<0x38280000>;
952 def STX_B : STORE_3R<0x38100000>;
953 def STX_H : STORE_3R<0x38140000>;
954 def STX_W : STORE_3R<0x38180000>;
955 def STX_D : STORE_3R<0x381c0000>;
956 def LDPTR_W : LOAD_2RI14<0x24000000>;
957 def LDPTR_D : LOAD_2RI14<0x26000000>;
958 def STPTR_W : STORE_2RI14<0x25000000>;
959 def STPTR_D : STORE_2RI14<0x27000000>;
960 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
965 def LDGT_B : LOAD_3R<0x38780000>;
966 def LDGT_H : LOAD_3R<0x38788000>;
967 def LDGT_W : LOAD_3R<0x38790000>;
968 def LDGT_D : LOAD_3R<0x38798000>;
969 def LDLE_B : LOAD_3R<0x387a0000>;
970 def LDLE_H : LOAD_3R<0x387a8000>;
971 def LDLE_W : LOAD_3R<0x387b0000>;
972 def LDLE_D : LOAD_3R<0x387b8000>;
973 def STGT_B : STORE_3R<0x387c0000>;
974 def STGT_H : STORE_3R<0x387c8000>;
975 def STGT_W : STORE_3R<0x387d0000>;
976 def STGT_D : STORE_3R<0x387d8000>;
977 def STLE_B : STORE_3R<0x387e0000>;
978 def STLE_H : STORE_3R<0x387e8000>;
979 def STLE_W : STORE_3R<0x387f0000>;
980 def STLE_D : STORE_3R<0x387f8000>;
983 def AMSWAP_B : AM_3R<0x385c0000>;
984 def AMSWAP_H : AM_3R<0x385c8000>;
985 def AMSWAP_W : AM_3R<0x38600000>;
986 def AMSWAP_D : AM_3R<0x38608000>;
987 def AMADD_B : AM_3R<0x385d0000>;
988 def AMADD_H : AM_3R<0x385d8000>;
989 def AMADD_W : AM_3R<0x38610000>;
990 def AMADD_D : AM_3R<0x38618000>;
991 def AMAND_W : AM_3R<0x38620000>;
992 def AMAND_D : AM_3R<0x38628000>;
993 def AMOR_W : AM_3R<0x38630000>;
994 def AMOR_D : AM_3R<0x38638000>;
995 def AMXOR_W : AM_3R<0x38640000>;
996 def AMXOR_D : AM_3R<0x38648000>;
997 def AMMAX_W : AM_3R<0x38650000>;
998 def AMMAX_D : AM_3R<0x38658000>;
999 def AMMIN_W : AM_3R<0x38660000>;
1000 def AMMIN_D : AM_3R<0x38668000>;
1001 def AMMAX_WU : AM_3R<0x38670000>;
1002 def AMMAX_DU : AM_3R<0x38678000>;
1003 def AMMIN_WU : AM_3R<0x38680000>;
1004 def AMMIN_DU : AM_3R<0x38688000>;
1005 def AMSWAP__DB_B : AM_3R<0x385e0000>;
1006 def AMSWAP__DB_H : AM_3R<0x385e8000>;
1007 def AMSWAP__DB_W : AM_3R<0x38690000>;
1008 def AMSWAP__DB_D : AM_3R<0x38698000>;
1009 def AMADD__DB_B : AM_3R<0x385f0000>;
1010 def AMADD__DB_H : AM_3R<0x385f8000>;
1011 def AMADD__DB_W : AM_3R<0x386a0000>;
1012 def AMADD__DB_D : AM_3R<0x386a8000>;
1013 def AMAND__DB_W : AM_3R<0x386b0000>;
1014 def AMAND__DB_D : AM_3R<0x386b8000>;
1015 def AMOR__DB_W : AM_3R<0x386c0000>;
1016 def AMOR__DB_D : AM_3R<0x386c8000>;
1017 def AMXOR__DB_W : AM_3R<0x386d0000>;
1018 def AMXOR__DB_D : AM_3R<0x386d8000>;
1019 def AMMAX__DB_W : AM_3R<0x386e0000>;
1020 def AMMAX__DB_D : AM_3R<0x386e8000>;
1021 def AMMIN__DB_W : AM_3R<0x386f0000>;
1022 def AMMIN__DB_D : AM_3R<0x386f8000>;
1023 def AMMAX__DB_WU : AM_3R<0x38700000>;
1024 def AMMAX__DB_DU : AM_3R<0x38708000>;
1025 def AMMIN__DB_WU : AM_3R<0x38710000>;
1026 def AMMIN__DB_DU : AM_3R<0x38718000>;
1027 def AMCAS_B : AM_3R<0x38580000>;
1028 def AMCAS_H : AM_3R<0x38588000>;
1029 def AMCAS_W : AM_3R<0x38590000>;
1030 def AMCAS_D : AM_3R<0x38598000>;
1031 def AMCAS__DB_B : AM_3R<0x385a0000>;
1032 def AMCAS__DB_H : AM_3R<0x385a8000>;
1033 def AMCAS__DB_W : AM_3R<0x385b0000>;
1034 def AMCAS__DB_D : AM_3R<0x385b8000>;
1035 def LL_D : LLBase<0x22000000>;
1036 def SC_D : SCBase<0x23000000>;
1037 def SC_Q : SCBase_128<0x38570000>;
1038 def LLACQ_D : LLBase_ACQ<0x38578800>;
1039 def SCREL_D : SCBase_REL<0x38578C00>;
1042 def CRC_W_B_W : ALU_3R<0x00240000>;
1043 def CRC_W_H_W : ALU_3R<0x00248000>;
1044 def CRC_W_W_W : ALU_3R<0x00250000>;
1045 def CRC_W_D_W : ALU_3R<0x00258000>;
1046 def CRCC_W_B_W : ALU_3R<0x00260000>;
1047 def CRCC_W_H_W : ALU_3R<0x00268000>;
1048 def CRCC_W_W_W : ALU_3R<0x00270000>;
1049 def CRCC_W_D_W : ALU_3R<0x00278000>;
1052 def ASRTLE_D : FmtASRT<0x00010000, (outs), (ins GPR:$rj, GPR:$rk),
1054 def ASRTGT_D : FmtASRT<0x00018000, (outs), (ins GPR:$rj, GPR:$rk),
1056 def RDTIME_D : RDTIME_2R<0x00006800>;
1088 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0));
1098 : ComplexPattern<GRLenVT, 1, "selectShiftMaskGRLen", [], [], 0>;
1099 def shiftMask32 : ComplexPattern<i64, 1, "selectShiftMask32", [], [], 0>;
1168 def : Pat<(i64 (mul (loongarch_bstrpick GPR:$rj, (i64 31), (i64 0)),
1169 (loongarch_bstrpick GPR:$rk, (i64 31), (i64 0)))),
1308 // We lower `debugtrap` to `break 0`, as this is guaranteed to exist and work,
1311 // every other project uses the generic immediate of 0 for this.
1312 def : Pat<(debugtrap), (BREAK 0)>;
1355 (i64 31), (i64 0)),
1388 def : Pat<(sext_inreg GPR:$rj, i32), (ADDI_W GPR:$rj, 0)>;
1400 def : Pat<(seteq GPR:$rj, 0), (SLTUI GPR:$rj, 1)>;
1410 def : Pat<(setne GPR:$rj, 0), (SLTU R0, GPR:$rj)>;
1429 def : Pat<(select GPR:$cond, GPR:$t, 0), (MASKEQZ GPR:$t, GPR:$cond)>;
1430 def : Pat<(select GPR:$cond, 0, GPR:$f), (MASKNEZ GPR:$f, GPR:$cond)>;
1462 def : Pat<(brcond (GRLenVT (seteq GPR:$rj, 0)), bb:$imm21),
1464 def : Pat<(brcond (GRLenVT (setne GPR:$rj, 0)), bb:$imm21),
1475 def : Pat<(brind GPR:$rj), (PseudoBRIND GPR:$rj, 0)>;
1511 PseudoInstExpansion<(JIRL R1, GPR:$rj, 0)>;
1517 let isCall = 1, hasSideEffects = 0, mayStore = 0, mayLoad = 0, Defs = [R1] in
1524 PseudoInstExpansion<(JIRL R0, R1, 0)>;
1562 PseudoInstExpansion<(JIRL R0, GPR:$rj, 0)>;
1569 hasSideEffects = 0, mayStore = 0, mayLoad = 0, Uses = [R3] in
1574 hasSideEffects = 0, mayStore = 0, mayLoad = 0, Uses = [R3] in
1580 let isCall = 1, isBarrier = 1, isCodeGenOnly = 0, isAsmParserOnly = 1,
1581 Defs = [R1], Size = 8, hasSideEffects = 0, mayStore = 0, mayLoad = 0 in
1586 isCodeGenOnly = 0, isAsmParserOnly = 1, Size = 8, hasSideEffects = 0,
1587 mayStore = 0, mayLoad = 0 in
1596 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0 in {
1609 // Define isCodeGenOnly = 0 to expose them to tablegened assembly parser.
1610 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,
1640 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0,
1659 let isCall = 1, isBarrier = 1, hasSideEffects = 0, mayStore = 0, mayLoad = 0,
1666 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0,
1679 let isCall = 1, isBarrier = 1, hasSideEffects = 0, mayStore = 0, mayLoad = 0,
1680 isCodeGenOnly = 0, isAsmParserOnly = 1, Defs = [R1, R4, R20], Size = 32 in
1776 def : Pat<(vt (LoadOp BaseAddr:$rj)), (Inst BaseAddr:$rj, 0)>;
1820 (Inst StTy:$rd, BaseAddr:$rj, 0)>;
1865 // - Bit 4: kind of constraint (0: completion, 1: ordering)
1866 // - Bit 3: barrier for previous read (0: true, 1: false)
1867 // - Bit 2: barrier for previous write (0: true, 1: false)
1868 // - Bit 1: barrier for succeeding read (0: true, 1: false)
1869 // - Bit 0: barrier for succeeding write (0: true, 1: false)
1871 // Hint 0x700: barrier for "read after read" from the same address, which is
1872 // e.g. needed by LL-SC loops on older models. (DBAR 0x700 behaves the same as
1878 // all as the full barrier (DBAR 0), so we can unconditionally start emiting the
1881 def : Pat<(atomic_fence 4, timm), (DBAR 0b10100)>; // acquire
1882 def : Pat<(atomic_fence 5, timm), (DBAR 0b10010)>; // release
1883 def : Pat<(atomic_fence 6, timm), (DBAR 0b10000)>; // acqrel
1884 def : Pat<(atomic_fence 7, timm), (DBAR 0b10000)>; // seqcst
1942 let hasSideEffects = 0;
1956 let hasSideEffects = 0;
1989 let hasSideEffects = 0;
2004 let hasSideEffects = 0;
2019 let hasSideEffects = 0;
2033 let hasSideEffects = 0;
2227 def : InstAlias<"nop", (ANDI R0, R0, 0)>;
2231 def : InstAlias<"ret", (JIRL R0, R1, 0)>;
2232 def : InstAlias<"jr $rj", (JIRL R0, GPR:$rj, 0)>;
2240 (BLT GPR:$rd, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
2242 (BLTU GPR:$rd, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
2244 (BGE GPR:$rd, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
2246 (BGEU GPR:$rd, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
2248 (BLT GPR:$rd, R0, simm16_lsl2_br:$imm16), 0>;
2250 (BLT R0, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
2252 (BGE R0, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
2254 (BGE GPR:$rd, R0, simm16_lsl2_br:$imm16), 0>;
2257 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,
2285 def CSRRD : FmtCSR<0x04000000, (outs GPR:$rd), (ins uimm14:$csr_num),
2288 def CSRWR : FmtCSR<0x04000020, (outs GPR:$dst),
2290 def CSRXCHG : FmtCSRXCHG<0x04000000, (outs GPR:$dst),
2296 def IOCSRRD_B : IOCSRRD<0x06480000>;
2297 def IOCSRRD_H : IOCSRRD<0x06480400>;
2298 def IOCSRRD_W : IOCSRRD<0x06480800>;
2299 def IOCSRWR_B : IOCSRWR<0x06481000>;
2300 def IOCSRWR_H : IOCSRWR<0x06481400>;
2301 def IOCSRWR_W : IOCSRWR<0x06481800>;
2303 def IOCSRRD_D : IOCSRRD<0x06480c00>;
2304 def IOCSRWR_D : IOCSRWR<0x06481c00>;
2308 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
2309 def TLBSRCH : FmtI32<0x06482800>;
2310 def TLBRD : FmtI32<0x06482c00>;
2311 def TLBWR : FmtI32<0x06483000>;
2312 def TLBFILL : FmtI32<0x06483400>;
2313 def TLBCLR : FmtI32<0x06482000>;
2314 def TLBFLUSH : FmtI32<0x06482400>;
2317 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
2320 def LDDIR : Fmt2RI8<0x06400000, (outs GPR:$rd),
2326 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
2327 def ERTN : FmtI32<0x06483800>;
2328 def DBCL : MISC_I15<0x002a8000>;
2329 def IDLE : MISC_I15<0x06488000>;