Lines Matching full:loongarch
1 //=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===//
9 // This file contains the LoongArch implementation of the TargetInstrInfo class.
14 #include "LoongArch.h"
28 : LoongArchGenInstrInfo(LoongArch::ADJCALLSTACKDOWN, in LoongArchInstrInfo()
29 LoongArch::ADJCALLSTACKUP), in LoongArchInstrInfo()
33 return MCInstBuilder(LoongArch::ANDI) in getNop()
34 .addReg(LoongArch::R0) in getNop()
35 .addReg(LoongArch::R0) in getNop()
43 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
44 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg) in copyPhysReg()
46 .addReg(LoongArch::R0); in copyPhysReg()
51 if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
52 BuildMI(MBB, MBBI, DL, get(LoongArch::VORI_B), DstReg) in copyPhysReg()
59 if (LoongArch::LASX256RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
60 BuildMI(MBB, MBBI, DL, get(LoongArch::XVORI_B), DstReg) in copyPhysReg()
67 if (LoongArch::CFRRegClass.contains(DstReg) && in copyPhysReg()
68 LoongArch::GPRRegClass.contains(SrcReg)) { in copyPhysReg()
69 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVGR2CF), DstReg) in copyPhysReg()
74 if (LoongArch::GPRRegClass.contains(DstReg) && in copyPhysReg()
75 LoongArch::CFRRegClass.contains(SrcReg)) { in copyPhysReg()
76 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVCF2GR), DstReg) in copyPhysReg()
81 if (LoongArch::CFRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
82 BuildMI(MBB, MBBI, DL, get(LoongArch::PseudoCopyCFR), DstReg) in copyPhysReg()
89 if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
90 Opc = LoongArch::FMOV_S; in copyPhysReg()
91 } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
92 Opc = LoongArch::FMOV_D; in copyPhysReg()
93 } else if (LoongArch::GPRRegClass.contains(DstReg) && in copyPhysReg()
94 LoongArch::FPR32RegClass.contains(SrcReg)) { in copyPhysReg()
96 Opc = LoongArch::MOVFR2GR_S; in copyPhysReg()
97 } else if (LoongArch::GPRRegClass.contains(DstReg) && in copyPhysReg()
98 LoongArch::FPR64RegClass.contains(SrcReg)) { in copyPhysReg()
100 Opc = LoongArch::MOVFR2GR_D; in copyPhysReg()
118 if (LoongArch::GPRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
119 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32 in storeRegToStackSlot()
120 ? LoongArch::ST_W in storeRegToStackSlot()
121 : LoongArch::ST_D; in storeRegToStackSlot()
122 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
123 Opcode = LoongArch::FST_S; in storeRegToStackSlot()
124 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
125 Opcode = LoongArch::FST_D; in storeRegToStackSlot()
126 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
127 Opcode = LoongArch::VST; in storeRegToStackSlot()
128 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
129 Opcode = LoongArch::XVST; in storeRegToStackSlot()
130 else if (LoongArch::CFRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
131 Opcode = LoongArch::PseudoST_CFR; in storeRegToStackSlot()
156 if (LoongArch::GPRRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
157 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32 in loadRegFromStackSlot()
158 ? LoongArch::LD_W in loadRegFromStackSlot()
159 : LoongArch::LD_D; in loadRegFromStackSlot()
160 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
161 Opcode = LoongArch::FLD_S; in loadRegFromStackSlot()
162 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
163 Opcode = LoongArch::FLD_D; in loadRegFromStackSlot()
164 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
165 Opcode = LoongArch::VLD; in loadRegFromStackSlot()
166 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
167 Opcode = LoongArch::XVLD; in loadRegFromStackSlot()
168 else if (LoongArch::CFRRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
169 Opcode = LoongArch::PseudoLD_CFR; in loadRegFromStackSlot()
187 Register SrcReg = LoongArch::R0; in movImm()
197 case LoongArch::LU12I_W: in movImm()
202 case LoongArch::ADDI_W: in movImm()
203 case LoongArch::ORI: in movImm()
204 case LoongArch::LU32I_D: // "rj" is needed due to InstrInfo pattern in movImm()
205 case LoongArch::LU52I_D: in movImm()
237 case LoongArch::ADDI_D: in isAsCheapAsAMove()
238 case LoongArch::ORI: in isAsCheapAsAMove()
239 case LoongArch::XORI: in isAsCheapAsAMove()
241 MI.getOperand(1).getReg() == LoongArch::R0) || in isAsCheapAsAMove()
332 case LoongArch::BEQ: in isBranchOffsetInRange()
333 case LoongArch::BNE: in isBranchOffsetInRange()
334 case LoongArch::BLT: in isBranchOffsetInRange()
335 case LoongArch::BGE: in isBranchOffsetInRange()
336 case LoongArch::BLTU: in isBranchOffsetInRange()
337 case LoongArch::BGEU: in isBranchOffsetInRange()
339 case LoongArch::BEQZ: in isBranchOffsetInRange()
340 case LoongArch::BNEZ: in isBranchOffsetInRange()
341 case LoongArch::BCEQZ: in isBranchOffsetInRange()
342 case LoongArch::BCNEZ: in isBranchOffsetInRange()
344 case LoongArch::B: in isBranchOffsetInRange()
345 case LoongArch::PseudoBR: in isBranchOffsetInRange()
392 "LoongArch branch conditions have at most two components!"); in insertBranch()
396 MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(TBB); in insertBranch()
415 MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(FBB); in insertBranch()
442 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in insertIndirectBranch()
446 *BuildMI(MBB, II, DL, get(LoongArch::PCALAU12I), ScratchReg) in insertIndirectBranch()
450 get(STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W), in insertIndirectBranch()
454 BuildMI(MBB, II, DL, get(LoongArch::PseudoBRIND)) in insertIndirectBranch()
460 LoongArch::GPRRegClass, PCALAU12I.getIterator(), /*RestoreAfter=*/false, in insertIndirectBranch()
462 if (Scav != LoongArch::NoRegister) in insertIndirectBranch()
467 Scav = LoongArch::R20; in insertIndirectBranch()
472 &LoongArch::GPRRegClass, TRI, Register()); in insertIndirectBranch()
478 &LoongArch::GPRRegClass, TRI, Register()); in insertIndirectBranch()
490 case LoongArch::BEQ: in getOppositeBranchOpc()
491 return LoongArch::BNE; in getOppositeBranchOpc()
492 case LoongArch::BNE: in getOppositeBranchOpc()
493 return LoongArch::BEQ; in getOppositeBranchOpc()
494 case LoongArch::BEQZ: in getOppositeBranchOpc()
495 return LoongArch::BNEZ; in getOppositeBranchOpc()
496 case LoongArch::BNEZ: in getOppositeBranchOpc()
497 return LoongArch::BEQZ; in getOppositeBranchOpc()
498 case LoongArch::BCEQZ: in getOppositeBranchOpc()
499 return LoongArch::BCNEZ; in getOppositeBranchOpc()
500 case LoongArch::BCNEZ: in getOppositeBranchOpc()
501 return LoongArch::BCEQZ; in getOppositeBranchOpc()
502 case LoongArch::BLT: in getOppositeBranchOpc()
503 return LoongArch::BGE; in getOppositeBranchOpc()
504 case LoongArch::BGE: in getOppositeBranchOpc()
505 return LoongArch::BLT; in getOppositeBranchOpc()
506 case LoongArch::BLTU: in getOppositeBranchOpc()
507 return LoongArch::BGEU; in getOppositeBranchOpc()
508 case LoongArch::BGEU: in getOppositeBranchOpc()
509 return LoongArch::BLTU; in getOppositeBranchOpc()
530 {MO_CALL, "loongarch-call"}, in getSerializableDirectMachineOperandTargetFlags()
531 {MO_CALL_PLT, "loongarch-call-plt"}, in getSerializableDirectMachineOperandTargetFlags()
532 {MO_PCREL_HI, "loongarch-pcrel-hi"}, in getSerializableDirectMachineOperandTargetFlags()
533 {MO_PCREL_LO, "loongarch-pcrel-lo"}, in getSerializableDirectMachineOperandTargetFlags()
534 {MO_PCREL64_LO, "loongarch-pcrel64-lo"}, in getSerializableDirectMachineOperandTargetFlags()
535 {MO_PCREL64_HI, "loongarch-pcrel64-hi"}, in getSerializableDirectMachineOperandTargetFlags()
536 {MO_GOT_PC_HI, "loongarch-got-pc-hi"}, in getSerializableDirectMachineOperandTargetFlags()
537 {MO_GOT_PC_LO, "loongarch-got-pc-lo"}, in getSerializableDirectMachineOperandTargetFlags()
538 {MO_GOT_PC64_LO, "loongarch-got-pc64-lo"}, in getSerializableDirectMachineOperandTargetFlags()
539 {MO_GOT_PC64_HI, "loongarch-got-pc64-hi"}, in getSerializableDirectMachineOperandTargetFlags()
540 {MO_LE_HI, "loongarch-le-hi"}, in getSerializableDirectMachineOperandTargetFlags()
541 {MO_LE_LO, "loongarch-le-lo"}, in getSerializableDirectMachineOperandTargetFlags()
542 {MO_LE64_LO, "loongarch-le64-lo"}, in getSerializableDirectMachineOperandTargetFlags()
543 {MO_LE64_HI, "loongarch-le64-hi"}, in getSerializableDirectMachineOperandTargetFlags()
544 {MO_IE_PC_HI, "loongarch-ie-pc-hi"}, in getSerializableDirectMachineOperandTargetFlags()
545 {MO_IE_PC_LO, "loongarch-ie-pc-lo"}, in getSerializableDirectMachineOperandTargetFlags()
546 {MO_IE_PC64_LO, "loongarch-ie-pc64-lo"}, in getSerializableDirectMachineOperandTargetFlags()
547 {MO_IE_PC64_HI, "loongarch-ie-pc64-hi"}, in getSerializableDirectMachineOperandTargetFlags()
548 {MO_DESC_PC_HI, "loongarch-desc-pc-hi"}, in getSerializableDirectMachineOperandTargetFlags()
549 {MO_DESC_PC_LO, "loongarch-desc-pc-lo"}, in getSerializableDirectMachineOperandTargetFlags()
550 {MO_DESC64_PC_LO, "loongarch-desc64-pc-lo"}, in getSerializableDirectMachineOperandTargetFlags()
551 {MO_DESC64_PC_HI, "loongarch-desc64-pc-hi"}, in getSerializableDirectMachineOperandTargetFlags()
552 {MO_DESC_LD, "loongarch-desc-ld"}, in getSerializableDirectMachineOperandTargetFlags()
553 {MO_DESC_CALL, "loongarch-desc-call"}, in getSerializableDirectMachineOperandTargetFlags()
554 {MO_LD_PC_HI, "loongarch-ld-pc-hi"}, in getSerializableDirectMachineOperandTargetFlags()
555 {MO_GD_PC_HI, "loongarch-gd-pc-hi"}}; in getSerializableDirectMachineOperandTargetFlags()
560 bool LoongArch::isSEXT_W(const MachineInstr &MI) { in isSEXT_W()
561 return MI.getOpcode() == LoongArch::ADDI_W && MI.getOperand(1).isReg() && in isSEXT_W()