Lines Matching full:loongarch
1 //=- LoongArchISelDAGToDAG.cpp - A dag to dag inst selector for LoongArch -===//
9 // This file defines an instruction selector for the LoongArch target.
22 #define DEBUG_TYPE "loongarch-isel"
23 #define PASS_NAME "LoongArch DAG->DAG Pattern Instruction Selection"
56 LoongArch::R0, GRLenVT); in INITIALIZE_PASS()
61 SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT); in INITIALIZE_PASS()
65 if (Inst.Opc == LoongArch::LU12I_W) in INITIALIZE_PASS()
66 Result = CurDAG->getMachineNode(LoongArch::LU12I_W, DL, GRLenVT, SDImm); in INITIALIZE_PASS()
80 Subtarget->is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in INITIALIZE_PASS()
114 Op = Is256Vec ? LoongArch::PseudoXVREPLI_B : LoongArch::PseudoVREPLI_B; in INITIALIZE_PASS()
118 Op = Is256Vec ? LoongArch::PseudoXVREPLI_H : LoongArch::PseudoVREPLI_H; in INITIALIZE_PASS()
122 Op = Is256Vec ? LoongArch::PseudoXVREPLI_W : LoongArch::PseudoVREPLI_W; in INITIALIZE_PASS()
126 Op = Is256Vec ? LoongArch::PseudoXVREPLI_D : LoongArch::PseudoVREPLI_D; in INITIALIZE_PASS()
219 Base = CurDAG->getRegister(LoongArch::R0, VT); in SelectAddrConstant()
234 // Shift instructions on LoongArch only read the lower 5 or 6 bits of the in selectShiftMask()
277 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, LoongArch::R0, VT); in selectShiftMask()
278 unsigned NegOpc = VT == MVT::i64 ? LoongArch::SUB_D : LoongArch::SUB_W; in selectShiftMask()
419 // This pass converts a legalized DAG into a LoongArch-specific DAG, ready