Lines Matching +full:invert +full:- +full:ext
1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
55 #define DEBUG_TYPE "lanai-lower"
68 "lanai-constant-mul-threshold", cl::Hidden,
152 // statements. Re-evaluate this on new benchmarks. in LanaiTargetLowering()
160 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores in LanaiTargetLowering()
162 MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores in LanaiTargetLowering()
164 MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores in LanaiTargetLowering()
209 //===----------------------------------------------------------------------===//
211 //===----------------------------------------------------------------------===//
280 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
296 if (isInt<16>(C->getSExtValue())) { in LowerAsmOperandForConstraint()
297 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C), in LowerAsmOperandForConstraint()
306 if (C->getZExtValue() == 0) { in LowerAsmOperandForConstraint()
314 if (isUInt<16>(C->getZExtValue())) { in LowerAsmOperandForConstraint()
315 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C), in LowerAsmOperandForConstraint()
323 if (C->getZExtValue() <= 31) { in LowerAsmOperandForConstraint()
324 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C), in LowerAsmOperandForConstraint()
332 int64_t Val = C->getSExtValue(); in LowerAsmOperandForConstraint()
341 int64_t Val = C->getSExtValue(); in LowerAsmOperandForConstraint()
342 if ((Val >= -33554432) && (Val <= 33554431)) { in LowerAsmOperandForConstraint()
360 //===----------------------------------------------------------------------===//
362 //===----------------------------------------------------------------------===//
433 // LowerCCCArguments - transform physical registers into virtual registers and
464 // If this is an 8/16-bit value, it is really passed promoted to 32 in LowerCCCArguments()
465 // bits. Insert an assert[sz]ext to capture this, then truncate to the in LowerCCCArguments()
511 Register Reg = LanaiMFI->getSRetReturnReg(); in LowerCCCArguments()
514 LanaiMFI->setSRetReturnReg(Reg); in LowerCCCArguments()
524 LanaiMFI->setVarArgsFrameIndex(FI); in LowerCCCArguments()
545 // CCValAssign - represent the assignment of the return value to a location in LowerReturn()
548 // CCState - Info about the registers and stack slot. in LowerReturn()
577 Register Reg = LanaiMFI->getSRetReturnReg(); in LowerReturn()
600 // LowerCCCCallTo - functions arguments are copied from virtual regs to
617 const Function *CalleeFn = dyn_cast<Function>(G->getGlobal()); in LowerCCCCallTo()
619 NumFixedArgs = CalleeFn->getFunctionType()->getNumParams(); in LowerCCCCallTo()
717 // Build a sequence of copy-to-reg nodes chained together with token chain and in LowerCCCCallTo()
728 // Likewise ExternalSymbol -> TargetExternalSymbol. in LowerCCCCallTo()
732 G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag); in LowerCCCCallTo()
735 E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag); in LowerCCCCallTo()
744 // Add a register mask operand representing the call-preserved registers. in LowerCCCCallTo()
745 // TODO: Should return-twice functions be handled? in LowerCCCCallTo()
747 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv); in LowerCCCCallTo()
774 // LowerCallResult - Lower the result values of a call into the
799 //===----------------------------------------------------------------------===//
801 //===----------------------------------------------------------------------===//
805 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); in IntCondCCodeToICC()
816 if (RHSC->getZExtValue() == 0xFFFFFFFF) { in IntCondCCodeToICC()
817 // X > -1 -> X >= 0 -> is_plus(X) in IntCondCCodeToICC()
826 if (RHSC->getZExtValue() == 0) in IntCondCCodeToICC()
827 // X < 0 -> is_minus(X) in IntCondCCodeToICC()
834 if (RHSC->getZExtValue() == 0xFFFFFFFF) { in IntCondCCodeToICC()
835 // X <= -1 -> X < 0 -> is_minus(X) in IntCondCCodeToICC()
844 if (RHSC->getZExtValue() == 0) in IntCondCCodeToICC()
845 // X >= 0 -> is_plus(X) in IntCondCCodeToICC()
886 EVT VT = Op->getValueType(0); in LowerMUL()
890 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in LowerMUL()
894 int64_t MulAmt = C->getSExtValue(); in LowerMUL()
895 int32_t HighestOne = -1; in LowerMUL()
899 // Convert to non-adjacent form (NAF) signed-digit representation. in LowerMUL()
900 // NAF is a signed-digit form where no adjacent digits are non-zero. It is the in LowerMUL()
902 // digits will be non-zero vs 1/2 for regular binary representation). And as in LowerMUL()
903 // the non-zero digits will be the only digits contributing to the instruction in LowerMUL()
906 // choosing the non-zero coefficients such that the resulting quotient is in LowerMUL()
909 int S = (MulAmt < 0 ? -1 : 1); in LowerMUL()
914 ZI = 2 - (E % 4); in LowerMUL()
921 E = (E - ZI) / 2; in LowerMUL()
927 // Start by assuming a shift and a add/sub for every non-zero entry (hence in LowerMUL()
928 // every non-zero entry requires 1 shift and 1 add/sub except for the first in LowerMUL()
930 int32_t InstrRequired = 2 * NonzeroEntries - 1; in LowerMUL()
931 // Correct possible over-adding due to shift by 0 (which is not emitted). in LowerMUL()
933 --InstrRequired; in LowerMUL()
940 SDValue V = Op->getOperand(0); in LowerMUL()
945 if (HighestOne == -1) in LowerMUL()
964 else if (SignedDigit[I] == -1) in LowerMUL()
1008 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), in LowerVASTART()
1013 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); in LowerVASTART()
1064 const unsigned Offset = -4; in LowerRETURNADDR()
1071 // Mark it an implicit live-in. in LowerRETURNADDR()
1072 Register Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
1085 while (Depth--) { in LowerFRAMEADDR()
1086 const unsigned Offset = -8; in LowerFRAMEADDR()
1130 const Constant *C = N->getConstVal(); in LowerConstantPool()
1136 // then assume address will fit in 21-bits. in LowerConstantPool()
1138 TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) { in LowerConstantPool()
1140 C, MVT::i32, N->getAlign(), N->getOffset(), LanaiII::MO_NO_FLAG); in LowerConstantPool()
1148 SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(), in LowerConstantPool()
1149 N->getOffset(), OpFlagHi); in LowerConstantPool()
1150 SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(), in LowerConstantPool()
1151 N->getOffset(), OpFlagLo); in LowerConstantPool()
1162 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); in LowerGlobalAddress()
1163 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); in LowerGlobalAddress()
1170 // section, then assume address will fit in 21-bits. in LowerGlobalAddress()
1171 const GlobalObject *GO = GV->getAliaseeObject(); in LowerGlobalAddress()
1172 if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) { in LowerGlobalAddress()
1196 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); in LowerBlockAddress()
1214 // If the code model is small assume address will fit in 21-bits. in LowerJumpTable()
1217 JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG); in LowerJumpTable()
1226 JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi); in LowerJumpTable()
1228 JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo); in LowerJumpTable()
1247 // LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt)) in LowerSHL_PARTS()
1249 // Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi) in LowerSHL_PARTS()
1296 // r_high = (32 - b <= 0) ? 0 : r_high; in LowerSRL_PARTS()
1299 // r_low = (32 - b <= 0) ? r_high : r_low; in LowerSRL_PARTS()
1300 // r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b)); in LowerSRL_PARTS()
1337 // (select cc -1, y) [AllOnes=1]
1338 // (select cc y, -1) [AllOnes=1]
1342 // * Invert is set when N is the all zero/ones constant when CC is false.
1346 // * X = 0, Invert = False and OtherOp = Y
1347 // * Y = 0, Invert = True and OtherOp = X
1349 bool &Invert, SDValue &OtherOp, in isConditionalZeroOrAllOnes() argument
1351 switch (N->getOpcode()) { in isConditionalZeroOrAllOnes()
1355 CC = N->getOperand(0); in isConditionalZeroOrAllOnes()
1356 SDValue N1 = N->getOperand(1); in isConditionalZeroOrAllOnes()
1357 SDValue N2 = N->getOperand(2); in isConditionalZeroOrAllOnes()
1359 Invert = false; in isConditionalZeroOrAllOnes()
1364 Invert = true; in isConditionalZeroOrAllOnes()
1374 CC = N->getOperand(0); in isConditionalZeroOrAllOnes()
1378 EVT VT = N->getValueType(0); in isConditionalZeroOrAllOnes()
1380 Invert = true; in isConditionalZeroOrAllOnes()
1384 CC = N->getOperand(0); in isConditionalZeroOrAllOnes()
1388 EVT VT = N->getValueType(0); in isConditionalZeroOrAllOnes()
1389 Invert = !AllOnes; in isConditionalZeroOrAllOnes()
1403 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1404 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1405 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
1406 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
1407 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
1414 // (add (zext cc), x) -> (select cc (add x, 1), x)
1415 // (add (sext cc), x) -> (select cc (add x, -1), x)
1422 EVT VT = N->getValueType(0); in combineSelectAndUse()
1433 DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal); in combineSelectAndUse()
1445 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative()
1446 SDValue N1 = N->getOperand(1); in combineSelectAndUseCommutative()
1447 if (N0.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
1450 if (N1.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
1456 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1459 SDValue N0 = N->getOperand(0); in PerformSUBCombine()
1460 SDValue N1 = N->getOperand(1); in PerformSUBCombine()
1462 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) in PerformSUBCombine()
1463 if (N1.getNode()->hasOneUse()) in PerformSUBCombine()
1472 switch (N->getOpcode()) { in PerformDAGCombine()
1501 Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1); in computeKnownBitsForTargetNode()
1502 Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1); in computeKnownBitsForTargetNode()