1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
36     EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true),
37                   cl::desc("Enable Hexagon constant-extender optimization"));
39 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true),
40                                   cl::desc("Enable RDF-based optimizations"));
43     "rdf-bb-limit", cl::Hidden, cl::init(1000),
47     DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden,
51     DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
55     DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
56                          cl::desc("Disable Hexagon CFG Optimization"));
59     DisableHCP("disable-hcp", cl::Hidden,
62 static cl::opt<bool> DisableStoreWidening("disable-store-widen", cl::Hidden,
66 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
70 static cl::opt<bool> EnableTfrCleanup("hexagon-tfr-cleanup", cl::init(true),
74 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
75                                    cl::desc("Enable early if-conversion"));
77 static cl::opt<bool> EnableCopyHoist("hexagon-copy-hoist", cl::init(true),
82     EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden,
86     EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden,
90     EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden,
94     "hexagon-mux", cl::init(true), cl::Hidden,
98     EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden,
103     EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
107     DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
111     EnableGenMemAbs("hexagon-mem-abs", cl::init(true), cl::Hidden,
114 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
118 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
122 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden,
126     EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
130     EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true),
134     EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true),
138     "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true),
139     cl::desc("Simplify the CFG after atomic expansion pass"));
141 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
145 /// HexagonTargetMachineModule - Note that this is used on hosts that
156   DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());  in createVLIWMachineSched()
157   DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());  in createVLIWMachineSched()
158   DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());  in createVLIWMachineSched()
159   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));  in createVLIWMachineSched()
261                                            StringRef CPU, StringRef FS,  in HexagonTargetMachine()  argument
271           "e-m:e-p:32:32:32-a:0-n16:32-"  in HexagonTargetMachine()
272           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"  in HexagonTargetMachine()
273           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",  in HexagonTargetMachine()
274           TT, CPU, FS, Options, getEffectiveRelocModel(RM),  in HexagonTargetMachine()
278       Subtarget(Triple(TT), CPU, FS, *this) {  in HexagonTargetMachine()
289   Attribute CPUAttr = FnAttrs.getFnAttr("target-cpu");  in getSubtargetImpl()
290   Attribute FSAttr = FnAttrs.getFnAttr("target-features");  in getSubtargetImpl()
292   std::string CPU =  in getSubtargetImpl()  local
297   // the "unsafe-fp-math" function attribute.  in getSubtargetImpl()
299   // exists to make "unsafe-fp-math" force creating a new subtarget.  in getSubtargetImpl()
301   if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())  in getSubtargetImpl()
302     FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;  in getSubtargetImpl()
304   auto &I = SubtargetMap[CPU + FS];  in getSubtargetImpl()
310     I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);  in getSubtargetImpl()
420     // Rotate loops to expose bit-simplification opportunities.  in addInstSelector()
461   if (TM->getOptLevel() >= CodeGenOptLevel::Default)  in addPreRegAlloc()