Lines Matching refs:HexagonSubtarget
76 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, in HexagonSubtarget() function in HexagonSubtarget
90 HexagonSubtarget &
91 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { in initializeSubtargetDependencies()
172 bool HexagonSubtarget::isHVXElementType(MVT Ty, bool IncludeBool) const { in isHVXElementType()
183 bool HexagonSubtarget::isHVXVectorType(EVT VecTy, bool IncludeBool) const { in isHVXVectorType()
211 bool HexagonSubtarget::isTypeForHVX(Type *VecTy, bool IncludeBool) const { in isTypeForHVX()
246 void HexagonSubtarget::UsrOverflowMutation::apply(ScheduleDAGInstrs *DAG) { in apply()
259 void HexagonSubtarget::HVXMemLatencyMutation::apply(ScheduleDAGInstrs *DAG) { in apply()
298 bool HexagonSubtarget::CallMutation::shouldTFRICallBind( in shouldTFRICallBind()
310 void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAGInstrs) { in apply()
319 auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); in apply()
378 void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) { in apply()
428 bool HexagonSubtarget::useAA() const { in useAA()
436 void HexagonSubtarget::adjustSchedDependency( in adjustSchedDependency()
513 void HexagonSubtarget::getPostRAMutations( in getPostRAMutations()
520 void HexagonSubtarget::getSMSMutations( in getSMSMutations()
527 void HexagonSubtarget::anchor() {} in anchor()
529 bool HexagonSubtarget::enableMachineScheduler() const { in enableMachineScheduler()
535 bool HexagonSubtarget::usePredicatedCalls() const { in usePredicatedCalls()
539 int HexagonSubtarget::updateLatency(MachineInstr &SrcInst, in updateLatency()
554 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const { in restoreLatency()
603 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) in changeLatency()
632 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst, in isBestZeroLatency()
717 unsigned HexagonSubtarget::getL1CacheLineSize() const { in getL1CacheLineSize()
721 unsigned HexagonSubtarget::getL1PrefetchDistance() const { in getL1PrefetchDistance()
725 bool HexagonSubtarget::enableSubRegLiveness() const { return true; } in enableSubRegLiveness()
727 Intrinsic::ID HexagonSubtarget::getIntrinsicId(unsigned Opc) const { in getIntrinsicId()