Lines Matching refs:Kill
647 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
650 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
660 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
766 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg()); in splitExt()
806 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
831 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
834 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
837 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) in splitShift()
843 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) in splitShift()
854 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR) in splitShift()
865 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR)); in splitShift()
877 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
880 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR); in splitShift()
883 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR)) in splitShift()
941 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR) in splitAslOr()
942 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR); in splitAslOr()
948 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR) in splitAslOr()
949 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
953 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
970 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR); in splitAslOr()
981 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR); in splitAslOr()