Lines Matching full:rs
46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
120 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_lo)>;
121 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_hi)>;
246 def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>;
247 def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>;
248 def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>;
249 def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>;
250 def ToAext64: OutPatFrag<(ops node:$Rs),
251 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>;
253 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
254 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>;
279 def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>;
280 def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>;
281 def Sext64: PatLeaf<(i64 Usxtw:$Rs)>;
283 def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>;
284 def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>;
286 def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off),
287 (PS_fi (i32 AddrFI:$Rs), imm:$off)>;
323 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;
327 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)),
328 (MI RegPred:$Rs, imm:$I)>;
332 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
333 (MI RsPred:$Rs, RtPred:$Rt)>;
337 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)),
338 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>;
342 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
343 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
492 def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>;
493 def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>;
494 def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>;
495 def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>;
496 def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>;
498 def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>;
499 def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>;
500 def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>;
502 def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>;
503 def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i I32:$Rs, 0)>;
504 def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>;
507 def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>;
508 def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>;
538 def: Pat<(v4i16 (azext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>;
539 def: Pat<(v2i32 (azext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
540 def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>;
541 def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>;
543 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
544 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
546 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
547 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
551 def: Pat<(v4i8 (trunc V4I16:$Rs)),
552 (S2_vtrunehb V4I16:$Rs)>;
562 def: Pat<(v2i16 (trunc V2I32:$Rs)),
563 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
566 def: Pat<(v2i1 (trunc V2I32:$Rs)),
567 (A4_vcmpweqi (A2_andp V2I32:$Rs, (A2_combineii (i32 1), (i32 1))),
569 def: Pat<(v4i1 (trunc V4I16:$Rs)),
570 (A4_vcmpheqi (Combinew (A2_andir (HiReg $Rs), (i32 0x00010001)),
571 (A2_andir (LoReg $Rs), (i32 0x00010001))),
573 def: Pat<(v8i1 (trunc V8I8:$Rs)),
574 (A4_vcmpbeqi (Combinew (A2_andir (HiReg $Rs), (i32 0x01010101)),
575 (A2_andir (LoReg $Rs), (i32 0x01010101))),
582 def: Pat<(i32 (ssat I32:$Rs, i8)), (A2_satb I32:$Rs)>;
583 def: Pat<(i32 (ssat I32:$Rs, i16)), (A2_sath I32:$Rs)>;
584 def: Pat<(i32 (ssat I64:$Rs, i32)), (A2_sat I64:$Rs)>;
585 def: Pat<(i32 (usat I32:$Rs, i8)), (A2_satub I32:$Rs)>;
586 def: Pat<(i32 (usat I32:$Rs, i16)), (A2_satuh I32:$Rs)>;
587 def: Pat<(i32 (usat I64:$Rs, i32)),
588 (C2_mux (C2_cmpeqi (HiReg $Rs), (i32 0)), (LoReg $Rs), (i32 -1))>;
590 def: Pat<(v4i8 (ssat V4I16:$Rs, v4i8)), (S2_vsathb V4I16:$Rs)>;
591 def: Pat<(v2i16 (ssat V2I32:$Rs, v2i16)), (S2_vsatwh V2I32:$Rs)>;
592 def: Pat<(v4i8 (usat V4I16:$Rs, v4i8)), (S2_vsathub V4I16:$Rs)>;
593 def: Pat<(v2i16 (usat V2I32:$Rs, v2i16)), (S2_vsatwuh V2I32:$Rs)>;
661 def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)),
662 (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>;
663 def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)),
664 (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>;
666 def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)),
667 (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>;
668 def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)),
669 (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>;
744 def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)),
745 (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>;
746 def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)),
747 (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>;
748 def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)),
749 (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>;
753 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
754 (Output RsPred:$Rs, RtPred:$Rt)>;
757 : OutPatFrag<(ops node:$Rs, node:$Rt),
758 (C2_not (MI $Rs, $Rt))>;
787 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)),
788 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
789 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)),
790 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
791 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)),
792 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
793 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)),
794 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
804 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
805 (MI I32:$Rs, imm:$I)>;
806 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
807 (MI I32:$Rs, imm:$I)>;
812 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
813 (C2_not (MI I32:$Rs, imm:$I))>;
814 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
815 (C2_not (MI I32:$Rs, imm:$I))>;
820 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)),
821 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>;
822 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)),
823 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>;
837 def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))),
838 (A4_rcmpeq I32:$Rs, I32:$Rt)>;
839 def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))),
840 (A4_rcmpneq I32:$Rs, I32:$Rt)>;
841 def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))),
842 (A4_rcmpeqi I32:$Rs, imm:$s8)>;
843 def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))),
844 (A4_rcmpneqi I32:$Rs, imm:$s8)>;
877 : OutPatFrag<(ops node:$Rs, node:$Rt),
878 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
913 def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt),
914 (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>;
915 def: Pat<(select I1:$Pu, v4i8:$Rs, v4i8:$Rt),
916 (C2_mux I1:$Pu, v4i8:$Rs, v4i8:$Rt)>;
917 def: Pat<(select I1:$Pu, v2i16:$Rs, v2i16:$Rt),
918 (C2_mux I1:$Pu, v2i16:$Rs, v2i16:$Rt)>;
919 def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs),
920 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
921 def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8),
922 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>;
926 def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt),
927 (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>;
930 def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs),
931 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>;
932 def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8),
933 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
937 def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt),
938 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
939 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
941 def: Pat<(select I1:$Pu, v2i32:$Rs, v2i32:$Rt),
942 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
943 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
945 def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I),
946 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>;
949 def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt),
950 (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>;
951 def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt),
952 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
953 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
955 def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt),
956 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>;
957 def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt),
958 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>;
960 def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs),
961 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>;
965 def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt),
966 (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>;
967 def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt),
968 (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>;
969 def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt),
970 (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>;
972 def: Pat<(vselect (pnot V8I1:$Pu), V8I8:$Rs, V8I8:$Rt),
973 (C2_vmux V8I1:$Pu, V8I8:$Rt, V8I8:$Rs)>;
974 def: Pat<(vselect (pnot V4I1:$Pu), V4I16:$Rs, V4I16:$Rt),
975 (C2_vmux V4I1:$Pu, V4I16:$Rt, V4I16:$Rs)>;
976 def: Pat<(vselect (pnot V2I1:$Pu), V2I32:$Rs, V2I32:$Rt),
977 (C2_vmux V2I1:$Pu, V2I32:$Rt, V2I32:$Rs)>;
1004 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)),
1005 IsPosHalf:$Rs, IsPosHalf:$Rt), i16),
1006 (InstA IntRegs:$Rs, IntRegs:$Rt)>;
1007 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)),
1008 IsPosHalf:$Rt, IsPosHalf:$Rs), i16),
1009 (InstB IntRegs:$Rs, IntRegs:$Rt)>;
1070 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2),
1071 (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>;
1072 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2),
1073 (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>;
1075 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off),
1076 (S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>;
1077 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off),
1078 (S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>;
1086 def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5),
1087 (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>;
1088 def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6),
1089 (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>;
1091 def: Pat<(HexagonEXTRACTU I32:$Rs, I32:$Width, I32:$Off),
1092 (S2_extractu_rp I32:$Rs, (Combinew $Width, $Off))>;
1093 def: Pat<(HexagonEXTRACTU I64:$Rs, I32:$Width, I32:$Off),
1094 (S2_extractup_rp I64:$Rs, (Combinew $Width, $Off))>;
1107 def: Pat<(v4i8 (splat_vector I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
1108 def: Pat<(v2i16 (splat_vector I32:$Rs)), (LoReg (S2_vsplatrh I32:$Rs))>;
1109 def: Pat<(v4i16 (splat_vector I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
1110 def: Pat<(v2i32 (splat_vector I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>;
1113 def: Pat<(v8i8 (splat_vector I32:$Rs)), (S6_vsplatrbp I32:$Rs)>,
1115 def: Pat<(v8i8 (splat_vector I32:$Rs)),
1116 (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>;
1119 def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 8, u5_0ImmPred:$U5), i8),
1120 (S4_extract I32:$Rs, 8, imm:$U5)>;
1121 def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 16, u5_0ImmPred:$U5), i16),
1122 (S4_extract I32:$Rs, 16, imm:$U5)>;
1123 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 8, u6_0ImmPred:$U6), i8),
1124 (S4_extractp I64:$Rs, 8, imm:$U6)>;
1125 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 16, u6_0ImmPred:$U6), i16),
1126 (S4_extractp I64:$Rs, 16, imm:$U6)>;
1127 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 32, u6_0ImmPred:$U6), i32),
1128 (S4_extractp I64:$Rs, 32, imm:$U6)>;
1131 def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 8, I32:$Off), i8),
1132 (S4_extract_rp I32:$Rs, (Combinew (ToI32 8), I32:$Off))>;
1133 def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 16, I32:$Off), i16),
1134 (S4_extract_rp I32:$Rs, (Combinew (ToI32 16), I32:$Off))>;
1135 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 8, I32:$Off), i8),
1136 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 8), I32:$Off))>;
1137 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 16, I32:$Off), i16),
1138 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 16), I32:$Off))>;
1139 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 32, I32:$Off), i32),
1140 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 32), I32:$Off))>;
1151 def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>;
1156 def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8),
1157 (A4_combineri IntRegs:$Rs, imm:$s8)>;
1158 def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs),
1159 (A4_combineir imm:$s8, IntRegs:$Rs)>;
1171 def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>;
1175 def: Pat<(bswap V2I16:$Rs), (A2_combine_lh (A2_swiz $Rs), (A2_swiz $Rs))>;
1176 def: Pat<(bswap V2I32:$Rs), (Combinew (A2_swiz (HiReg $Rs)),
1177 (A2_swiz (LoReg $Rs)))>;
1178 def: Pat<(bswap V4I16:$Rs), (A2_orp (S2_lsr_i_vh $Rs, 8),
1179 (S2_asl_i_vh $Rs, 8))>;
1182 def: Pat<(shl I32:$Rs, (i32 16)), (A2_aslh I32:$Rs)>;
1183 def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>;
1216 def FShl32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S),
1217 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>;
1218 def FShl32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru),
1219 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>;
1221 def FShl64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S),
1222 (S2_lsr_i_p_or (S2_asl_i_p $Rs, $S), $Rt, (Subi<64> $S))>;
1223 def FShl64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru),
1224 (S2_lsr_r_p_or (S2_asl_r_p $Rs, $Ru), $Rt, (A2_subri 64, $Ru))>;
1234 def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)),
1235 (A2_combine_lh I32:$Rs, I32:$Rt)>;
1236 def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S),
1237 (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>;
1245 def: Pat<(rotl I32:$Rs, u5_0ImmPred:$S), (FShl32i $Rs, $Rs, imm:$S)>;
1246 def: Pat<(rotl I64:$Rs, u6_0ImmPred:$S), (FShl64i $Rs, $Rs, imm:$S)>;
1247 def: Pat<(fshl I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShl32i $Rs, $Rt, imm:$S)>;
1248 def: Pat<(fshl I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShl64i $Rs, $Rt, imm:$S)>;
1250 def: Pat<(rotl I32:$Rs, I32:$Rt), (FShl32r $Rs, $Rs, $Rt)>;
1251 def: Pat<(rotl I64:$Rs, I32:$Rt), (FShl64r $Rs, $Rs, $Rt)>;
1252 def: Pat<(fshl I32:$Rs, I32:$Rt, I32:$Ru), (FShl32r $Rs, $Rt, $Ru)>;
1253 def: Pat<(fshl I64:$Rs, I64:$Rt, I32:$Ru), (FShl64r $Rs, $Rt, $Ru)>;
1256 def FShr32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S),
1257 (LoReg (S2_lsr_i_p (Combinew $Rs, $Rt), $S))>;
1258 def FShr32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru),
1259 (LoReg (S2_lsr_r_p (Combinew $Rs, $Rt), $Ru))>;
1261 def FShr64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S),
1262 (S2_asl_i_p_or (S2_lsr_i_p $Rt, $S), $Rs, (Subi<64> $S))>;
1263 def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru),
1264 (S2_asl_r_p_or (S2_lsr_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>;
1268 def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)),
1269 (A2_combine_lh I32:$Rs, I32:$Rt)>;
1270 def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S),
1271 (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>;
1275 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (S6_rol_i_r I32:$Rs, (Subi<32> $S))>;
1276 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (S6_rol_i_p I64:$Rs, (Subi<64> $S))>;
1279 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (FShr32i $Rs, $Rs, imm:$S)>;
1280 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (FShr64i $Rs, $Rs, imm:$S)>;
1281 def: Pat<(fshr I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShr32i $Rs, $Rt, imm:$S)>;
1282 def: Pat<(fshr I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShr64i $Rs, $Rt, imm:$S)>;
1284 def: Pat<(rotr I32:$Rs, I32:$Rt), (FShr32r $Rs, $Rs, $Rt)>;
1285 def: Pat<(rotr I64:$Rs, I32:$Rt), (FShr64r $Rs, $Rs, $Rt)>;
1286 def: Pat<(fshr I32:$Rs, I32:$Rt, I32:$Ru), (FShr32r $Rs, $Rt, $Ru)>;
1287 def: Pat<(fshr I64:$Rs, I64:$Rt, I32:$Ru), (FShr64r $Rs, $Rt, $Ru)>;
1290 def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)),
1291 (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>;
1292 def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)),
1293 (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>;
1297 def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)),
1298 (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>;
1388 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
1389 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>;
1416 def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))),
1417 (A2_combine_ll I32:$Rt, I32:$Rs)>;
1418 def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))),
1419 (A2_combine_lh I32:$Rt, I32:$Rs)>;
1420 def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))),
1421 (A2_combine_hl I32:$Rt, I32:$Rs)>;
1422 def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))),
1423 (A2_combine_hh I32:$Rt, I32:$Rs)>;
1464 def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S),
1465 (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>;
1466 def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S),
1467 (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>;
1468 def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S),
1469 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>;
1470 def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt),
1471 (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>;
1472 def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt),
1473 (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>;
1474 def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt),
1475 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>;
1481 def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>;
1482 def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>;
1483 def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>;
1484 def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>;
1485 def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>;
1487 def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>;
1488 def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>;
1490 def: Pat<(fabs F64:$Rs),
1491 (Combinew (S2_clrbit_i (HiReg $Rs), 31),
1492 (i32 (LoReg $Rs)))>;
1493 def: Pat<(fneg F64:$Rs),
1494 (Combinew (S2_togglebit_i (HiReg $Rs), 31),
1495 (i32 (LoReg $Rs)))>;
1497 def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>;
1498 def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>;
1499 def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>;
1500 def: Pat<(sub anyimm:$s10, I32:$Rs), (A2_subri imm:$s10, I32:$Rs)>;
1572 def DfMpy: OutPatFrag<(ops node:$Rs, node:$Rt),
1576 (F2_dfmpyll $Rs, $Rt),
1577 $Rs, $Rt),
1578 $Rt, $Rs),
1579 $Rs, $Rt)>;
1582 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>;
1588 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt),
1589 (F2_dfmpyfix $Rt, $Rs))>;
1617 OutPatFrag<(ops node:$Rs, node:$Rt), (S2_vtrunohb (M5_vmpybuu $Rs, $Rt))>;
1628 def: Pat<(v4i8 (mulhu V4I8:$Rs, V4I8:$Rt)), (Mulhub4 $Rs, $Rt)>;
1638 def: Pat<(v4i8 (mulhs V4I8:$Rs, V4I8:$Rt)),
1639 (LoReg (Mulhsb8 (v8i8 (ToAext64 $Rs)), (v8i8 (ToAext64 $Rt))))>;
1644 OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 $Rs, $Rt)>;
1647 OutPatFrag<(ops node:$Rs, node:$Rt),
1648 (A2_combine_hh (HiReg (Muli16 $Rs, $Rt)),
1649 (LoReg (Muli16 $Rs, $Rt)))>;
1655 def: Pat<(v2i16 (mulhs V2I16:$Rs, V2I16:$Rt)), (Mulhsh2 $Rs, $Rt)>;
1658 def: Pat<(v2i16 (mulhu V2I16:$Rs, V2I16:$Rt)),
1660 (Mulhsh2 $Rs, $Rt),
1661 (A2_svaddh (LoReg (A2_andp (Combinew $Rt, $Rs),
1662 (S2_asr_i_vh (Combinew $Rs, $Rt), 15))),
1663 (HiReg (A2_andp (Combinew $Rt, $Rs),
1664 (S2_asr_i_vh (Combinew $Rs, $Rt), 15)))))>;
1673 def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)),
1674 (M2_mpysin IntRegs:$Rs, imm:$u8)>;
1681 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
1682 def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8),
1683 (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>;
1685 def: Pat<(add Sext64:$Rs, I64:$Rt),
1686 (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>;
1711 def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)),
1712 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>;
1713 def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)),
1714 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>;
1715 def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)),
1716 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
1717 def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru),
1718 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
1719 def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6),
1720 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
1727 def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)),
1728 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>;
1729 def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)),
1730 (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>;
1733 def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))),
1734 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1735 def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))),
1736 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1738 def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)),
1739 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>;
1740 def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)),
1741 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>;
1742 def: Pat<(mul Sext64:$Rs, Sext64:$Rt),
1743 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1745 def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)),
1746 (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1747 def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)),
1748 (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
1749 def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))),
1750 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
1751 def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))),
1752 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
1753 def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))),
1754 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
1755 def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))),
1756 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>;
1759 def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16),
1760 (A2_addh_l16_ll I32:$Rt, I32:$Rs)>;
1761 def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)),
1762 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>;
1763 def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)),
1764 (A2_addh_h16_ll I32:$Rt, I32:$Rs)>;
1767 def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16),
1768 (A2_subh_l16_ll I32:$Rt, I32:$Rs)>;
1769 def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)),
1770 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>;
1771 def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)),
1772 (A2_subh_h16_ll I32:$Rt, I32:$Rs)>;
1828 def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6),
1829 (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>;
1830 def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6),
1831 (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>;
1836 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)),
1837 (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>;
1838 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)),
1839 (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>;
1840 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)),
1841 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>;
1844 def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx),
1845 (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>;
1846 def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx),
1847 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>;
1849 def: Pat<(mul V2I32:$Rs, V2I32:$Rt),
1850 (PS_vmulw V2I32:$Rs, V2I32:$Rt)>;
1851 def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)),
1852 (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>;
1856 def: Pat<(add V4I8:$Rs, V4I8:$Rt),
1857 (LoReg (A2_vaddub (ToAext64 $Rs), (ToAext64 $Rt)))>;
1858 def: Pat<(sub V4I8:$Rs, V4I8:$Rt),
1859 (LoReg (A2_vsubub (ToAext64 $Rs), (ToAext64 $Rt)))>;
1864 def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)),
1866 (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>;
1867 def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)),
1868 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)),
1869 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>;
1872 def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)),
1873 (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>;
1876 def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)),
1877 (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))),
1878 (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>;
1885 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
1889 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
1893 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
1897 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
1907 def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>;
1909 def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>;
1912 def: Pat<(bitreverse V4I8:$Rs), (A2_swiz (S2_brev $Rs))>;
1913 def: Pat<(bitreverse V8I8:$Rs), (Combinew (A2_swiz (LoReg (S2_brevp $Rs))),
1914 (A2_swiz (HiReg (S2_brevp $Rs))))>;
1915 def: Pat<(bitreverse V2I16:$Rs), (A2_combine_lh (S2_brev $Rs),
1916 (S2_brev $Rs))>;
1917 def: Pat<(bitreverse V4I16:$Rs),
1918 (Combinew (A2_combine_lh (LoReg (S2_brevp $Rs)),
1919 (LoReg (S2_brevp $Rs))),
1920 (A2_combine_lh (HiReg (S2_brevp $Rs)),
1921 (HiReg (S2_brevp $Rs))))>;
1922 def: Pat<(bitreverse V2I32:$Rs),
1923 (Combinew (i32 (LoReg (S2_brevp $Rs))),
1924 (i32 (HiReg (S2_brevp $Rs))))>;
1927 def: Pat<(and I32:$Rs, IsNPow2_32:$V),
1928 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>;
1929 def: Pat<(or I32:$Rs, IsPow2_32:$V),
1930 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>;
1931 def: Pat<(xor I32:$Rs, IsPow2_32:$V),
1932 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>;
1934 def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))),
1935 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1936 def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)),
1937 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1938 def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)),
1939 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
1968 def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)),
1969 (S2_tstbit_i IntRegs:$Rs, imm:$u5)>;
1970 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)),
1971 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1972 def: Pat<(i1 (trunc I32:$Rs)),
1973 (S2_tstbit_i IntRegs:$Rs, 0)>;
1974 def: Pat<(i1 (trunc I64:$Rs)),
1975 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
1978 def: Pat<(and (srl I32:$Rs, u5_0ImmPred:$u5), 1),
1979 (I1toI32 (S2_tstbit_i I32:$Rs, imm:$u5))>;
1985 def: Pat<(and (not (srl I32:$Rs, u5_0ImmPred:$u5)), 1),
1986 (I1toI32 (S4_ntstbit_i I32:$Rs, imm:$u5))>;
1993 def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)),
1994 (C2_bitsclri IntRegs:$Rs, imm:$u6)>;
1995 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)),
1996 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
2000 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)),
2001 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
2007 def: Pat<(HexagonTSTBIT I32:$Rs, u5_0ImmPred:$u5),
2008 (S2_tstbit_i I32:$Rs, imm:$u5)>;
2009 def: Pat<(HexagonTSTBIT I32:$Rs, I32:$Rt),
2010 (S2_tstbit_r I32:$Rs, I32:$Rt)>;
2016 def: Pat<(i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)),
2017 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>;
2018 def: Pat<(i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)),
2019 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>;
2020 def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)),
2021 (S4_ntstbit_r I32:$Rs, I32:$Rt)>;
2022 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)),
2023 (S2_tstbit_r I32:$Rs, I32:$Rt)>;
2026 def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64L:$u6), 0)),
2027 (S4_ntstbit_i (LoReg $Rs), (Log2_64 $u6))>;
2028 def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64H:$u6), 0)),
2029 (S4_ntstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 $u6))))>;
2030 def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64L:$u6), 0)),
2031 (S2_tstbit_i (LoReg $Rs), (Log2_64 imm:$u6))>;
2032 def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64H:$u6), 0)),
2033 (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 imm:$u6))))>;
2041 def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)),
2042 (C4_nbitsclri I32:$Rs, imm:$u6)>;
2043 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2044 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2045 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2046 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2053 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))),
2054 (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>;
2055 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))),
2056 (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>;
2057 def: Pat<(i32 (zext (i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)))),
2058 (I1toI32 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5)))>;
2059 def: Pat<(i32 (zext (i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)))),
2060 (I1toI32 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5)))>;
2061 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))),
2062 (I1toI32 (S4_ntstbit_r I32:$Rs, I32:$Rt))>;
2063 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))),
2064 (I1toI32 (S2_tstbit_r I32:$Rs, I32:$Rt))>;
2094 def L1toI32: OutPatFrag<(ops node:$Rs), (A2_subri 0, (i32 $Rs))>;
2095 def L1toI64: OutPatFrag<(ops node:$Rs), (ToSext64 (L1toI32 $Rs))>;
2118 // Patterns to select load-indexed: Rs + Off.
2129 // Patterns to select load-indexed: Rs + Off.
2133 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))),
2134 (VT (MI IntRegs:$Rs, imm:$Off))>;
2135 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))),
2136 (VT (MI IntRegs:$Rs, imm:$Off))>;
2137 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>;
2140 // Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi.
2147 // Patterns to select load reg indexed: Rs + Off with a value modifier.
2158 // Patterns to select load reg indexed: Rs + Off with a value modifier.
2162 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))),
2163 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
2164 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))),
2165 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
2166 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
2169 // Patterns to select load reg indexed: Rs + Off with a value modifier.
2177 // Pattern to select load reg reg-indexed: Rs + Rt<<u2.
2179 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))),
2180 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
2182 // Pattern to select load reg reg-indexed: Rs + Rt<<0.
2184 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))),
2185 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
2187 // Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier.
2190 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))),
2191 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>;
2193 // Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier.
2196 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))),
2197 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>;
2481 def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))),
2482 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
2483 def: Pat<(i1 (load I32:$Rs)),
2484 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
2508 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
2512 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
2513 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
2514 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)),
2515 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
2520 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)),
2521 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
2522 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)),
2523 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
2527 : Pat<(Store Value:$Rt, I32:$Rs),
2528 (MI IntRegs:$Rs, 0, Value:$Rt)>;
2535 : Pat<(Store Value:$Rs, AddrFI:$fi),
2536 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>;
2540 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
2541 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
2542 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)),
2543 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
2548 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)),
2549 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
2550 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)),
2551 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
2556 : Pat<(Store Value:$Rt, I32:$Rs),
2557 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
2580 : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))),
2581 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
2585 : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)),
2586 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>;
2682 def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)),
2683 (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>;
2775 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)),
2776 (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>;
2793 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)),
2794 (S4_storerb_rr IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>;
2933 def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)),
2934 (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>;
3032 def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs),
3033 (MI I32:$Rs, 0, I32:$A)>;
3035 def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs),
3036 (MI AddrFI:$Rs, 0, I32:$A)>;
3042 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A),
3043 (add I32:$Rs, ImmPred:$Off)),
3044 (MI I32:$Rs, imm:$Off, I32:$A)>;
3045 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), I32:$A),
3046 (IsOrAdd I32:$Rs, ImmPred:$Off)),
3047 (MI I32:$Rs, imm:$Off, I32:$A)>;
3049 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A),
3050 (add AddrFI:$Rs, ImmPred:$Off)),
3051 (MI AddrFI:$Rs, imm:$Off, I32:$A)>;
3052 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), I32:$A),
3053 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)),
3054 (MI AddrFI:$Rs, imm:$Off, I32:$A)>;
3131 def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs),
3132 (MI I32:$Rs, 0, (ArgMod Arg:$A))>;
3134 def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs),
3135 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>;
3142 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A),
3143 (add I32:$Rs, ImmPred:$Off)),
3144 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>;
3145 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), Arg:$A),
3146 (IsOrAdd I32:$Rs, ImmPred:$Off)),
3147 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>;
3149 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A),
3150 (add AddrFI:$Rs, ImmPred:$Off)),
3151 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>;
3152 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), Arg:$A),
3153 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)),
3154 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>;
3350 def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))),
3351 (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>;
3370 def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3),
3371 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>;
3372 def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)),
3373 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>;
3380 def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)),
3381 (PS_alloca IntRegs:$Rs, imm:$A)>;
3406 def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)),
3407 (S2_storew_locked I32:$Rs, I32:$Rt)>;
3408 def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)),
3409 (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>;
3410 def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)),
3411 (S4_stored_locked I32:$Rs, I64:$Rt)>;
3412 def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)),
3413 (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>;