Lines Matching refs:IntRegs
65 def : Pat <(store (v64i1 HvxQR:$src1), (i32 IntRegs:$addr)),
66 (V6_vS32b_ai IntRegs:$addr, 0,
70 def : Pat <(v64i1 (load (i32 IntRegs:$addr))),
72 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
74 def : Pat <(store (v128i1 HvxQR:$src1), (i32 IntRegs:$addr)),
75 (V6_vS32b_ai IntRegs:$addr, 0,
79 def : Pat <(v128i1 (load (i32 IntRegs:$addr))),
81 (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
86 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
87 (MI IntRegs:$src1)>;
115 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
116 (MI HvxWR:$src1, IntRegs:$src2)>;
118 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2),
119 (MI HvxWR:$src1, IntRegs:$src2)>;
123 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
124 (MI HvxVR:$src1, IntRegs:$src2)>;
126 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2),
127 (MI HvxVR:$src1, IntRegs:$src2)>;
155 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
156 (MI HvxQR:$src1, IntRegs:$src2)>;
158 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
159 (MI HvxQR:$src1, IntRegs:$src2)>;
171 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
172 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
175 IntRegs:$src3),
176 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
180 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
181 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
184 IntRegs:$src3),
185 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
189 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
190 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
193 IntRegs:$src3),
194 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
198 def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),
199 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
202 IntRegs:$src3),
203 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
234 def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
235 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
238 IntRegs:$src3),
239 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
244 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),
245 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
248 IntRegs:$src3),
249 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
262 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3),
263 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
266 IntRegs:$src2, imm:$src3),
267 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
271 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
272 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
275 IntRegs:$src3, imm:$src4),
276 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
280 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
281 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
284 HvxVR:$src3, IntRegs:$src4),
285 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
289 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
290 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
293 HvxVR:$src3, IntRegs:$src4),
294 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;