Lines Matching full:intid
84 multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
86 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
90 multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> {
91 def: Pat<(IntID HvxVR:$src1),
94 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1),
98 multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> {
99 def: Pat<(IntID HvxWR:$src1),
102 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1),
106 multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
107 def: Pat<(IntID HvxQR:$src1),
110 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1),
114 multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> {
115 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
118 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2),
122 multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> {
123 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
126 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2),
130 multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> {
131 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
134 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2),
138 multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> {
139 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
142 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
146 multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> {
147 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
150 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
154 multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> {
155 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
158 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
162 multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> {
163 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
166 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
170 multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> {
171 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
174 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
179 multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> {
180 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
183 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
188 multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> {
189 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
192 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
197 multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> {
198 def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),
201 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxWR:$src2,
206 multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> {
207 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),
210 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
215 multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> {
216 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
219 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
224 multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> {
225 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
228 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
233 multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> {
234 def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
237 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
243 multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> {
244 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),
247 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
252 multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> {
253 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
256 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1,
261 multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> {
262 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3),
265 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1,
270 multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> {
271 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
274 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
279 multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> {
280 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
283 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
288 multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> {
289 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
292 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,