Lines Matching full:src2
115 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
116 (MI HvxWR:$src1, IntRegs:$src2)>;
118 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2),
119 (MI HvxWR:$src1, IntRegs:$src2)>;
123 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
124 (MI HvxVR:$src1, IntRegs:$src2)>;
126 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2),
127 (MI HvxVR:$src1, IntRegs:$src2)>;
131 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
132 (MI HvxWR:$src1, HvxVR:$src2)>;
134 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2),
135 (MI HvxWR:$src1, HvxVR:$src2)>;
139 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
140 (MI HvxWR:$src1, HvxWR:$src2)>;
142 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
143 (MI HvxWR:$src1, HvxWR:$src2)>;
147 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
148 (MI HvxVR:$src1, HvxVR:$src2)>;
150 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
151 (MI HvxVR:$src1, HvxVR:$src2)>;
155 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
156 (MI HvxQR:$src1, IntRegs:$src2)>;
158 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
159 (MI HvxQR:$src1, IntRegs:$src2)>;
163 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
164 (MI HvxQR:$src1, HvxQR:$src2)>;
166 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
167 (MI HvxQR:$src1, HvxQR:$src2)>;
171 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
172 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
174 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
176 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
180 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
181 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
183 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
185 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
189 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
190 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
192 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
194 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
198 def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),
199 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
201 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxWR:$src2,
203 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
207 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),
208 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
210 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
212 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
216 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
217 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
219 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
221 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
225 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
226 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
228 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
230 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
234 def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
235 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
237 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
239 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
244 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),
245 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
247 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
249 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
253 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
254 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
257 HvxVR:$src2, imm:$src3),
258 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
262 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3),
263 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
266 IntRegs:$src2, imm:$src3),
267 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
271 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
272 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
274 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
276 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
280 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
281 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
283 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
285 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
289 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
290 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
292 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
294 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;