Lines Matching full:rs
12 : Pat <(IntID I32:$Rs),
13 (MI I32:$Rs)>;
16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
26 (A2_addi IntRegs:$Rs, imm:$s16)>;
27 def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt),
28 (A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
31 (A2_sub IntRegs:$Rs, IntRegs:$Rt)>;
32 def: Pat<(int_hexagon_A2_subri timm:$s10, IntRegs:$Rs),
33 (A2_subri imm:$s10, IntRegs:$Rs)>;
34 def: Pat<(int_hexagon_A2_subp DoubleRegs:$Rs, DoubleRegs:$Rt),
35 (A2_subp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
37 def: Pat<(int_hexagon_M2_mpyi IntRegs:$Rs, IntRegs:$Rt),
38 (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>;
39 def: Pat<(int_hexagon_M2_mpyui IntRegs:$Rs, IntRegs:$Rt), // Same as M2_mpyi
40 (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>;
41 def: Pat<(int_hexagon_M2_mpysmi IntRegs:$Rs, imm:$s9),
42 (M2_mpysmi IntRegs:$Rs, imm:$s9)>;
43 def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$Rs, IntRegs:$Rt),
44 (M2_dpmpyss_s0 IntRegs:$Rs, IntRegs:$Rt)>;
45 def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$Rs, IntRegs:$Rt),
46 (M2_dpmpyuu_s0 IntRegs:$Rs, IntRegs:$Rt)>;
48 def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$Rs, timm:$u5),
49 (S2_asl_i_r IntRegs:$Rs, imm:$u5)>;
50 def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$Rs, timm:$u5),
51 (S2_lsr_i_r IntRegs:$Rs, imm:$u5)>;
52 def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$Rs, timm:$u5),
53 (S2_asr_i_r IntRegs:$Rs, imm:$u5)>;
54 def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$Rs, timm:$u6),
55 (S2_asl_i_p DoubleRegs:$Rs, imm:$u6)>;
56 def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$Rs, timm:$u6),
57 (S2_lsr_i_p DoubleRegs:$Rs, imm:$u6)>;
58 def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$Rs, timm:$u6),
59 (S2_asr_i_p DoubleRegs:$Rs, imm:$u6)>;
61 def: Pat<(int_hexagon_A2_and IntRegs:$Rs, IntRegs:$Rt),
62 (A2_and IntRegs:$Rs, IntRegs:$Rt)>;
63 def: Pat<(int_hexagon_A2_andir IntRegs:$Rs, timm:$s10),
64 (A2_andir IntRegs:$Rs, imm:$s10)>;
65 def: Pat<(int_hexagon_A2_or IntRegs:$Rs, IntRegs:$Rt),
66 (A2_or IntRegs:$Rs, IntRegs:$Rt)>;
67 def: Pat<(int_hexagon_A2_orir IntRegs:$Rs, timm:$s10),
68 (A2_orir IntRegs:$Rs, imm:$s10)>;
69 def: Pat<(int_hexagon_A2_xor IntRegs:$Rs, IntRegs:$Rt),
70 (A2_xor IntRegs:$Rs, IntRegs:$Rt)>;
72 def: Pat<(int_hexagon_A2_sxtb IntRegs:$Rs),
73 (A2_sxtb IntRegs:$Rs)>;
74 def: Pat<(int_hexagon_A2_sxth IntRegs:$Rs),
75 (A2_sxth IntRegs:$Rs)>;
76 def: Pat<(int_hexagon_A2_zxtb IntRegs:$Rs),
77 (A2_zxtb IntRegs:$Rs)>;
78 def: Pat<(int_hexagon_A2_zxth IntRegs:$Rs),
79 (A2_zxth IntRegs:$Rs)>;
82 def : Pat <(int_hexagon_A2_not I32:$Rs),
83 (A2_subri -1, I32:$Rs)>;
86 def : Pat <(int_hexagon_A2_neg I32:$Rs),
87 (A2_subri 0, I32:$Rs)>;
92 def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, (i32 0)),
93 (A2_tfr I32:$Rs)>;
94 def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, (i32 0)),
95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
96 def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, (i32 0)),
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
98 def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, (i32 0)),
99 (S2_vsathub I64:$Rs)>;
102 def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, u5_0ImmPred_timm:$imm),
103 (S2_asr_i_r_rnd I32:$Rs, (UDEC1 u5_0ImmPred:$imm))>;
104 def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, u6_0ImmPred_timm:$imm),
105 (S2_asr_i_p_rnd I64:$Rs, (UDEC1 u6_0ImmPred:$imm))>;
106 def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, u4_0ImmPred_timm:$imm),
107 (S5_vasrhrnd I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
108 def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, u4_0ImmPred_timm:$imm),
109 (S5_asrhub_rnd_sat I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
177 def : Pat<(int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt),
178 (C2_tfrpr (S2_storew_locked I32:$Rs, I32:$Rt))>;
179 def : Pat<(int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt),
180 (C2_tfrpr (S4_stored_locked I32:$Rs, I64:$Rt))>;
187 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
188 (MI I32:$Rs, I32:$Ru, Val:$Rt)>;
197 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
198 (MI I32:$Rs, Imm:$s, I32:$Ru, Val:$Rt)>;