Lines Matching full:const
39 const HexagonSubtarget &Subtarget;
57 Register isLoadFromStackSlot(const MachineInstr &MI,
58 int &FrameIndex) const override;
65 Register isStoreToStackSlot(const MachineInstr &MI,
66 int &FrameIndex) const override;
72 const MachineInstr &MI,
73 SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
79 const MachineInstr &MI,
80 SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
109 bool AllowModify) const override;
115 int *BytesRemoved = nullptr) const override;
129 const DebugLoc &DL,
130 int *BytesAdded = nullptr) const override;
135 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
144 BranchProbability Probability) const override;
156 BranchProbability Probability) const override;
165 BranchProbability Probability) const override;
176 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
177 bool KillSrc) const override;
186 const TargetRegisterClass *RC,
187 const TargetRegisterInfo *TRI,
188 Register VReg) const override;
195 int FrameIndex, const TargetRegisterClass *RC,
196 const TargetRegisterInfo *TRI,
197 Register VReg) const override;
205 bool expandPostRAPseudo(MachineInstr &MI) const override;
209 const MachineInstr &LdSt,
210 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
212 const TargetRegisterInfo *TRI) const override;
217 const override;
221 MachineBasicBlock::iterator MI) const override;
224 bool isPredicated(const MachineInstr &MI) const override;
227 bool isPostIncrement(const MachineInstr &MI) const override;
232 ArrayRef<MachineOperand> Cond) const override;
237 ArrayRef<MachineOperand> Pred2) const override;
243 bool SkipDead) const override;
248 bool isPredicable(const MachineInstr &MI) const override;
252 bool isSchedulingBoundary(const MachineInstr &MI,
253 const MachineBasicBlock *MBB,
254 const MachineFunction &MF) const override;
259 const char *Str,
260 const MCAsmInfo &MAI,
261 const TargetSubtargetInfo *STI = nullptr) const override;
266 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
267 const ScheduleDAG *DAG) const override;
273 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
275 int64_t &Value) const override;
280 unsigned getInstrLatency(const InstrItineraryData *ItinData,
281 const MachineInstr &MI,
282 unsigned *PredCost = nullptr) const override;
286 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
293 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
294 const MachineInstr &MIb) const override;
298 bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
299 unsigned &OffsetPos) const override;
302 bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
312 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
313 const MachineInstr &DefMI,
315 const MachineInstr &UseMI,
316 unsigned UseIdx) const override;
321 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
328 ArrayRef<std::pair<unsigned, const char *>>
329 getSerializableDirectMachineOperandTargetFlags() const override;
336 ArrayRef<std::pair<unsigned, const char *>>
337 getSerializableBitmaskMachineOperandTargetFlags() const override;
339 bool isTailCall(const MachineInstr &MI) const override;
340 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
346 bool shouldSink(const MachineInstr &MI) const override;
350 Register createVR(MachineFunction *MF, MVT VT) const;
353 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
355 bool isAbsoluteSet(const MachineInstr &MI) const;
356 bool isAccumulator(const MachineInstr &MI) const;
357 bool isAddrModeWithOffset(const MachineInstr &MI) const;
358 bool isBaseImmOffset(const MachineInstr &MI) const;
359 bool isComplex(const MachineInstr &MI) const;
360 bool isCompoundBranchInstr(const MachineInstr &MI) const;
361 bool isConstExtended(const MachineInstr &MI) const;
362 bool isDeallocRet(const MachineInstr &MI) const;
363 bool isDependent(const MachineInstr &ProdMI,
364 const MachineInstr &ConsMI) const;
365 bool isDotCurInst(const MachineInstr &MI) const;
366 bool isDotNewInst(const MachineInstr &MI) const;
367 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
368 bool isEndLoopN(unsigned Opcode) const;
369 bool isExpr(unsigned OpType) const;
370 bool isExtendable(const MachineInstr &MI) const;
371 bool isExtended(const MachineInstr &MI) const;
372 bool isFloat(const MachineInstr &MI) const;
373 bool isHVXMemWithAIndirect(const MachineInstr &I,
374 const MachineInstr &J) const;
375 bool isIndirectCall(const MachineInstr &MI) const;
376 bool isIndirectL4Return(const MachineInstr &MI) const;
377 bool isJumpR(const MachineInstr &MI) const;
378 bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
379 bool isLateSourceInstr(const MachineInstr &MI) const;
380 bool isLoopN(const MachineInstr &MI) const;
381 bool isMemOp(const MachineInstr &MI) const;
382 bool isNewValue(const MachineInstr &MI) const;
383 bool isNewValue(unsigned Opcode) const;
384 bool isNewValueInst(const MachineInstr &MI) const;
385 bool isNewValueJump(const MachineInstr &MI) const;
386 bool isNewValueJump(unsigned Opcode) const;
387 bool isNewValueStore(const MachineInstr &MI) const;
388 bool isNewValueStore(unsigned Opcode) const;
389 bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
390 bool isPredicatedNew(const MachineInstr &MI) const;
391 bool isPredicatedNew(unsigned Opcode) const;
392 bool isPredicatedTrue(const MachineInstr &MI) const;
393 bool isPredicatedTrue(unsigned Opcode) const;
394 bool isPredicated(unsigned Opcode) const;
395 bool isPredicateLate(unsigned Opcode) const;
396 bool isPredictedTaken(unsigned Opcode) const;
397 bool isPureSlot0(const MachineInstr &MI) const;
398 bool isRestrictNoSlot1Store(const MachineInstr &MI) const;
399 bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
400 bool isSignExtendingLoad(const MachineInstr &MI) const;
401 bool isSolo(const MachineInstr &MI) const;
402 bool isSpillPredRegOp(const MachineInstr &MI) const;
403 bool isTC1(const MachineInstr &MI) const;
404 bool isTC2(const MachineInstr &MI) const;
405 bool isTC2Early(const MachineInstr &MI) const;
406 bool isTC4x(const MachineInstr &MI) const;
407 bool isToBeScheduledASAP(const MachineInstr &MI1,
408 const MachineInstr &MI2) const;
409 bool isHVXVec(const MachineInstr &MI) const;
410 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
412 const TargetRegisterInfo *TRI, bool Extend = true) const;
413 bool isVecAcc(const MachineInstr &MI) const;
414 bool isVecALU(const MachineInstr &MI) const;
415 bool isVecUsableNextPacket(const MachineInstr &ProdMI,
416 const MachineInstr &ConsMI) const;
417 bool isZeroExtendingLoad(const MachineInstr &MI) const;
419 bool addLatencyToSchedule(const MachineInstr &MI1,
420 const MachineInstr &MI2) const;
421 bool canExecuteInBundle(const MachineInstr &First,
422 const MachineInstr &Second) const;
423 bool doesNotReturn(const MachineInstr &CallMI) const;
424 bool hasEHLabel(const MachineBasicBlock *B) const;
425 bool hasNonExtEquivalent(const MachineInstr &MI) const;
426 bool hasPseudoInstrPair(const MachineInstr &MI) const;
427 bool hasUncondBranch(const MachineBasicBlock *B) const;
428 bool mayBeCurLoad(const MachineInstr &MI) const;
429 bool mayBeNewStore(const MachineInstr &MI) const;
430 bool producesStall(const MachineInstr &ProdMI,
431 const MachineInstr &ConsMI) const;
432 bool producesStall(const MachineInstr &MI,
433 MachineBasicBlock::const_instr_iterator MII) const;
434 bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const;
435 bool PredOpcodeHasJMP_c(unsigned Opcode) const;
436 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
438 unsigned getAddrMode(const MachineInstr &MI) const;
439 MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
440 LocationSize &AccessSize) const;
441 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
442 unsigned getCExtOpNum(const MachineInstr &MI) const;
444 getCompoundCandidateGroup(const MachineInstr &MI) const;
445 unsigned getCompoundOpcode(const MachineInstr &GA,
446 const MachineInstr &GB) const;
447 int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore = true) const;
448 int getCondOpcode(int Opc, bool sense) const;
449 int getDotCurOp(const MachineInstr &MI) const;
450 int getNonDotCurOp(const MachineInstr &MI) const;
451 int getDotNewOp(const MachineInstr &MI) const;
452 int getDotNewPredJumpOp(const MachineInstr &MI,
453 const MachineBranchProbabilityInfo *MBPI) const;
454 int getDotNewPredOp(const MachineInstr &MI,
455 const MachineBranchProbabilityInfo *MBPI) const;
456 int getDotOldOp(const MachineInstr &MI) const;
457 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
458 const;
459 short getEquivalentHWInstr(const MachineInstr &MI) const;
460 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
461 const MachineInstr &MI) const;
462 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
463 unsigned getInvertedPredicatedOpcode(const int Opc) const;
464 int getMaxValue(const MachineInstr &MI) const;
465 unsigned getMemAccessSize(const MachineInstr &MI) const;
466 int getMinValue(const MachineInstr &MI) const;
467 short getNonExtOpcode(const MachineInstr &MI) const;
469 unsigned &PredRegPos, unsigned &PredRegFlags) const;
470 short getPseudoInstrPair(const MachineInstr &MI) const;
471 short getRegForm(const MachineInstr &MI) const;
472 unsigned getSize(const MachineInstr &MI) const;
473 uint64_t getType(const MachineInstr &MI) const;
474 InstrStage::FuncUnits getUnits(const MachineInstr &MI) const;
476 MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const;
480 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
481 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
483 void immediateExtend(MachineInstr &MI) const;
485 MachineBasicBlock *NewTarget) const;
486 void genAllInsnTimingClasses(MachineFunction &MF) const;
487 bool reversePredSense(MachineInstr &MI) const;
488 unsigned reversePrediction(unsigned Opcode) const;
489 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
491 void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const;
492 bool getBundleNoShuf(const MachineInstr &MIB) const;
498 bool ToBigInstrs) const;
500 bool ToBigInstrs = true) const;
502 bool ToBigInstrs) const;
505 short changeAddrMode_abs_io(short Opc) const;
506 short changeAddrMode_io_abs(short Opc) const;
507 short changeAddrMode_io_pi(short Opc) const;
508 short changeAddrMode_io_rr(short Opc) const;
509 short changeAddrMode_pi_io(short Opc) const;
510 short changeAddrMode_rr_io(short Opc) const;
511 short changeAddrMode_rr_ur(short Opc) const;
512 short changeAddrMode_ur_rr(short Opc) const;
514 short changeAddrMode_abs_io(const MachineInstr &MI) const { in changeAddrMode_abs_io()
517 short changeAddrMode_io_abs(const MachineInstr &MI) const { in changeAddrMode_io_abs()
520 short changeAddrMode_io_rr(const MachineInstr &MI) const { in changeAddrMode_io_rr()
523 short changeAddrMode_rr_io(const MachineInstr &MI) const { in changeAddrMode_rr_io()
526 short changeAddrMode_rr_ur(const MachineInstr &MI) const { in changeAddrMode_rr_ur()
529 short changeAddrMode_ur_rr(const MachineInstr &MI) const { in changeAddrMode_ur_rr()
533 MCInst getNop() const override;