Lines Matching +full:mii +full:- +full:rt
1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
68 #define DEBUG_TYPE "hexagon-instrinfo"
76 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
77 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
80 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
84 "disable-hexagon-nv-schedule", cl::Hidden,
88 "enable-timing-class-latency", cl::Hidden, cl::init(false),
92 "enable-alu-forwarding", cl::Hidden, cl::init(true),
96 "enable-acc-forwarding", cl::Hidden, cl::init(true),
99 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
104 UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden,
109 const int Hexagon_MEMW_OFFSET_MIN = -4096;
111 const int Hexagon_MEMD_OFFSET_MIN = -8192;
113 const int Hexagon_MEMH_OFFSET_MIN = -2048;
115 const int Hexagon_MEMB_OFFSET_MIN = -1024;
117 const int Hexagon_ADDI_OFFSET_MIN = -32768;
147 if (!MIB->isDebugInstr()) in nonDbgMICount()
154 // to be constant-extendend it is not cheap since it occupies two slots
158 if (!(MI.getMF()->getFunction().hasOptSize())) in isAsCheapAsAMove()
168 // const-extended and hence, it is not cheap. in isAsCheapAsAMove()
195 /// Find the hardware loop instruction used to set-up the specified loop.
196 /// On Hexagon, we have two instructions used to set-up the hardware loop
212 // The loop set-up instruction will be in a predecessor block in findLoopInstr()
213 for (MachineBasicBlock *PB : BB->predecessors()) { in findLoopInstr()
219 for (MachineInstr &I : llvm::reverse(PB->instrs())) { in findLoopInstr()
285 /// isLoadFromStackSlot - If the specified machine instruction is a direct
333 /// isStoreToStackSlot - If the specified machine instruction is a direct
393 MachineBasicBlock::const_instr_iterator MII = MI.getIterator(); in hasLoadFromStackSlot() local
394 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII) in hasLoadFromStackSlot()
395 if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses)) in hasLoadFromStackSlot()
411 MachineBasicBlock::const_instr_iterator MII = MI.getIterator(); in hasStoreToStackSlot() local
412 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII) in hasStoreToStackSlot()
413 if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses)) in hasStoreToStackSlot()
429 /// HW-loop ENDLOOP:
433 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
463 --I; in analyzeBranch()
464 if (I->isEHLabel()) in analyzeBranch()
470 --I; in analyzeBranch()
472 while (I->isDebugInstr()) { in analyzeBranch()
475 --I; in analyzeBranch()
478 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump && in analyzeBranch()
479 I->getOperand(0).isMBB(); in analyzeBranch()
480 // Delete the J2_jump if it's equivalent to a fall-through. in analyzeBranch()
482 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { in analyzeBranch()
484 I->eraseFromParent(); in analyzeBranch()
488 --I; in analyzeBranch()
498 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) { in analyzeBranch()
507 --I; in analyzeBranch()
510 int LastOpcode = LastInst->getOpcode(); in analyzeBranch()
511 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0; in analyzeBranch()
514 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB()) in analyzeBranch()
517 !SecondLastInst->getOperand(0).isMBB()) in analyzeBranch()
523 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB()) in analyzeBranch()
529 TBB = LastInst->getOperand(0).getMBB(); in analyzeBranch()
533 TBB = LastInst->getOperand(0).getMBB(); in analyzeBranch()
534 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in analyzeBranch()
535 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
539 TBB = LastInst->getOperand(1).getMBB(); in analyzeBranch()
540 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in analyzeBranch()
541 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
544 // Only supporting rr/ri versions of new-value jumps. in analyzeBranch()
545 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) { in analyzeBranch()
546 TBB = LastInst->getOperand(2).getMBB(); in analyzeBranch()
547 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in analyzeBranch()
548 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
549 Cond.push_back(LastInst->getOperand(1)); in analyzeBranch()
561 if (!SecondLastInst->getOperand(1).isMBB()) in analyzeBranch()
563 TBB = SecondLastInst->getOperand(1).getMBB(); in analyzeBranch()
564 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in analyzeBranch()
565 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
566 FBB = LastInst->getOperand(0).getMBB(); in analyzeBranch()
570 // Only supporting rr/ri versions of new-value jumps. in analyzeBranch()
572 (SecondLastInst->getNumExplicitOperands() == 3) && in analyzeBranch()
574 TBB = SecondLastInst->getOperand(2).getMBB(); in analyzeBranch()
575 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in analyzeBranch()
576 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
577 Cond.push_back(SecondLastInst->getOperand(1)); in analyzeBranch()
578 FBB = LastInst->getOperand(0).getMBB(); in analyzeBranch()
585 TBB = SecondLastInst->getOperand(0).getMBB(); in analyzeBranch()
586 I = LastInst->getIterator(); in analyzeBranch()
588 I->eraseFromParent(); in analyzeBranch()
594 TBB = SecondLastInst->getOperand(0).getMBB(); in analyzeBranch()
595 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in analyzeBranch()
596 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
597 FBB = LastInst->getOperand(0).getMBB(); in analyzeBranch()
614 --I; in removeBranch()
615 if (I->isDebugInstr()) in removeBranch()
618 if (!I->isBranch()) in removeBranch()
620 if (Count && (I->getOpcode() == Hexagon::J2_jump)) in removeBranch()
673 Loop->getOperand(0).setMBB(TBB); in insertBranch()
704 "NV-jump cannot be inserted with another branch"); in insertBranch()
715 Loop->getOperand(0).setMBB(TBB); in insertBranch()
739 : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()), in HexagonPipelinerLoopInfo()
740 TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()), in HexagonPipelinerLoopInfo()
741 DL(Loop->getDebugLoc()) { in HexagonPipelinerLoopInfo()
742 // Inspect the Loop instruction up-front, as it may be deleted when we call in HexagonPipelinerLoopInfo()
744 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r in HexagonPipelinerLoopInfo()
745 ? -1 in HexagonPipelinerLoopInfo()
746 : Loop->getOperand(1).getImm(); in HexagonPipelinerLoopInfo()
747 if (TripCount == -1) in HexagonPipelinerLoopInfo()
748 LoopCount = Loop->getOperand(1).getReg(); in HexagonPipelinerLoopInfo()
759 if (TripCount == -1) { in createTripCountGreaterCondition()
761 Register Done = TII->createVR(MF, MVT::i1); in createTripCountGreaterCondition()
763 TII->get(Hexagon::C2_cmpgtui), Done) in createTripCountGreaterCondition()
767 Cond.push_back(NewCmp->getOperand(0)); in createTripCountGreaterCondition()
775 NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(), in setPreheader()
780 // If the loop trip count is a compile-time value, then just change the in adjustTripCount()
782 if (Loop->getOpcode() == Hexagon::J2_loop0i || in adjustTripCount()
783 Loop->getOpcode() == Hexagon::J2_loop1i) { in adjustTripCount()
784 int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust; in adjustTripCount()
786 Loop->getOperand(1).setImm(TripCount); in adjustTripCount()
790 // The loop trip count is a run-time value. We generate code to subtract in adjustTripCount()
792 Register LoopCount = Loop->getOperand(1).getReg(); in adjustTripCount()
793 Register NewLoopCount = TII->createVR(MF, MVT::i32); in adjustTripCount()
794 BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(), in adjustTripCount()
795 TII->get(Hexagon::A2_addi), NewLoopCount) in adjustTripCount()
798 Loop->getOperand(1).setReg(NewLoopCount); in adjustTripCount()
801 void disposed() override { Loop->eraseFromParent(); } in disposed()
808 MachineBasicBlock::iterator I = LoopBB->getFirstTerminator(); in analyzeLoopForPipelining()
810 if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) { in analyzeLoopForPipelining()
813 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs); in analyzeLoopForPipelining()
1046 /// expandPostRAPseudo - This function is called for all pseudo instructions
1079 return MMO->getAlign() >= NeedAlign; in expandPostRAPseudo()
1090 auto *Arr = cast<ConstantDataArray>(GV->getInitializer()); in expandPostRAPseudo()
1091 StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString(); in expandPostRAPseudo()
1127 std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI); in expandPostRAPseudo()
1135 .addImm(-MI.getOperand(1).getImm()); in expandPostRAPseudo()
1286 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies. in expandPostRAPseudo()
1310 // Expand 64-bit vector multiply with addition into 2 scalar multiplies. in expandPostRAPseudo()
1348 Register Rt = Op3.getReg(); in expandPostRAPseudo() local
1355 .addReg(Pu, (Rd == Rt) ? K1 : 0) in expandPostRAPseudo()
1357 if (Rd != Rt) in expandPostRAPseudo()
1360 .addReg(Rt, K3); in expandPostRAPseudo()
1638 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val"); in reverseBranchCondition()
1665 // Note: New-value stores are not included here as in the current
1684 // MI will need to be transformed into a predicated form. To avoid com- in PredicateInstruction()
1712 MI.removeOperand(n-1); in PredicateInstruction()
1713 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i) in PredicateInstruction()
1714 MI.addOperand(T->getOperand(i)); in PredicateInstruction()
1716 MachineBasicBlock::instr_iterator TI = T->getIterator(); in PredicateInstruction()
1719 MachineRegisterInfo &MRI = B.getParent()->getRegInfo(); in PredicateInstruction()
1812 for (auto *I : MBB->successors()) in isSchedulingBoundary()
1813 if (I->isEHPad()) in isSchedulingBoundary()
1835 /// Any other non-whitespace text is considered an instruction, with
1837 /// Variable-length instructions are not handled here; this function
2032 uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB); in areMemAccessesTriviallyDisjoint()
2036 uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA); in areMemAccessesTriviallyDisjoint()
2077 {MO_PCREL, "hexagon-pcrel"}, in getSerializableDirectMachineOperandTargetFlags()
2078 {MO_GOT, "hexagon-got"}, in getSerializableDirectMachineOperandTargetFlags()
2079 {MO_LO16, "hexagon-lo16"}, in getSerializableDirectMachineOperandTargetFlags()
2080 {MO_HI16, "hexagon-hi16"}, in getSerializableDirectMachineOperandTargetFlags()
2081 {MO_GPREL, "hexagon-gprel"}, in getSerializableDirectMachineOperandTargetFlags()
2082 {MO_GDGOT, "hexagon-gdgot"}, in getSerializableDirectMachineOperandTargetFlags()
2083 {MO_GDPLT, "hexagon-gdplt"}, in getSerializableDirectMachineOperandTargetFlags()
2084 {MO_IE, "hexagon-ie"}, in getSerializableDirectMachineOperandTargetFlags()
2085 {MO_IEGOT, "hexagon-iegot"}, in getSerializableDirectMachineOperandTargetFlags()
2086 {MO_TPREL, "hexagon-tprel"} in getSerializableDirectMachineOperandTargetFlags()
2096 {HMOTF_ConstExtended, "hexagon-ext"} in getSerializableBitmaskMachineOperandTargetFlags()
2102 MachineRegisterInfo &MRI = MF->getRegInfo(); in createVR()
2306 // - The OP code itself indicates that this is an extended instruction.
2307 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2710 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2718 // For scalars the auto-inc is s4 in isValidAutoIncImm()
2731 // For HVX vectors the auto-inc is s3 in isValidAutoIncImm()
2809 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass); in isValidOffset()
2811 if (Offset & (VectorSize-1)) in isValidOffset()
3078 if (!BaseOp || !BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
3098 Second.getOperand(Second.getNumOperands() - 1); in canExecuteInBundle()
3122 // Returns true if an instruction can be converted into a non-extended
3127 // of the extended operand, if so return that as the non-extended form. in hasNonExtEquivalent()
3132 // Check addressing mode and retrieve non-ext equivalent instruction. in hasNonExtEquivalent()
3166 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end(); in hasUncondBranch()
3168 if (I->isBarrier()) in hasUncondBranch()
3182 // Returns true, if a ST insn can be promoted to a new-value store.
3215 MachineBasicBlock::const_instr_iterator MII = BII; in producesStall() local
3216 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end(); in producesStall()
3218 if (!MII->isBundle()) in producesStall()
3219 return producesStall(*MII, MI); in producesStall()
3221 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) { in producesStall()
3222 const MachineInstr &J = *MII; in producesStall()
3240 // dot-new. in predCanBeUsedAsDotNew()
3381 --I; in getBranchingInstrs()
3382 if (I->isEHLabel()) in getBranchingInstrs()
3387 --I; in getBranchingInstrs()
3389 while (I->isDebugInstr()) { in getBranchingInstrs()
3392 --I; in getBranchingInstrs()
3403 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) { in getBranchingInstrs()
3412 --I; in getBranchingInstrs()
3459 (MI.getOperand(2).getImm() == -1))) in getCompoundCandidateGroup()
3512 // Returns -1 when there is no opcode found.
3519 return -1u; in getCompoundOpcode()
3522 return -1u; in getCompoundOpcode()
3524 return -1u; in getCompoundOpcode()
3525 // The value compared against must be either u5 or -1. in getCompoundOpcode()
3528 return -1u; in getCompoundOpcode()
3530 if (V == -1) in getCompoundOpcode()
3534 return -1u; in getCompoundOpcode()
3539 // Returns -1 if there is no opcode found.
3546 // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2. in getDuplexOpcode()
3588 return Iter->second; in getDuplexOpcode()
3594 return -1; in getDuplexOpcode()
3649 // store instruction to its .new predicated new-value form.
3651 // Note: It doesn't include conditional new-value stores as they can't be
3656 // / \ (not OK. it will cause new-value store to be
3670 // conditional new-value store becomes invalid when promoted to .new predicate
3676 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3679 // is not valid for new-value stores.
3686 // +---------------------+
3687 // /-----| if (p0) memw(..)=r0 |---------\~
3688 // || +---------------------+ ||
3693 // +-------------------------+ || +-------------------------+
3695 // +-------------------------+ || +-------------------------+
3702 // +-----------------------------+
3704 // +-----------------------------+
3708 // new-value stores.
3711 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3712 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3713 // 3) if (p0.new) memw(R0+#0) = R1 --->
3721 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3732 if (NVOpcode >= 0) // Valid new-value store instruction. in getDotNewOp()
3782 return MBPI->getEdgeProbability(Src, Dst); in getDotNewPredJumpOp()
3783 return BranchProbability(1, Src->succ_size()); in getDotNewPredJumpOp()
3792 // try to identify another target of this branch (potentially a fall- in getDotNewPredJumpOp()
3793 // -through) and check the probability of that target. in getDotNewPredJumpOp()
3796 // - one conditional branch, in getDotNewPredJumpOp()
3797 // - one conditional branch followed by one unconditional branch. in getDotNewPredJumpOp()
3798 // Otherwise, assume not-taken. in getDotNewPredJumpOp()
3821 // If this branch is the last, look for the fall-through block. in getDotNewPredJumpOp()
3829 assert(NextIt->isUnconditionalBranch()); in getDotNewPredJumpOp()
3832 for (const MachineOperand &Op : NextIt->operands()) { in getDotNewPredJumpOp()
3876 // All Hexagon architectures have prediction bits on dot-new branches, in getDotOldOp()
3877 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure in getDotOldOp()
3878 // to pick the right opcode when converting back to dot-old. in getDotOldOp()
3899 if (isNewValueStore(NewOp)) { // Convert into non-new-value format in getDotOldOp()
3901 assert(NewOp >= 0 && "Couldn't change new-value store to its old form."); in getDotOldOp()
3969 // Rd = memw(r29+#u5:2) - Handled above. in getDuplexCandidateGroup()
4020 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0 in getDuplexCandidateGroup()
4057 // memw(Rs+#u4:2) = Rt in getDuplexCandidateGroup()
4058 // memb(Rs+#u4:0) = Rt in getDuplexCandidateGroup()
4062 // memw(r29+#u5:2) = Rt in getDuplexCandidateGroup()
4070 // memw(Rs+#u4:2) = Rt in getDuplexCandidateGroup()
4078 // memb(Rs+#u4:0) = Rt in getDuplexCandidateGroup()
4088 // memh(Rs+#u3:1) = Rt in getDuplexCandidateGroup()
4089 // memw(r29+#u5:2) = Rt in getDuplexCandidateGroup()
4096 // memh(Rs+#u3:1) = Rt in getDuplexCandidateGroup()
4145 // Rd = #-1 in getDuplexCandidateGroup()
4154 // Rd = add(Rs,#-1) in getDuplexCandidateGroup()
4172 // Rd = add(Rs,#-1) in getDuplexCandidateGroup()
4175 (MI.getOperand(2).getImm() == -1))) in getDuplexCandidateGroup()
4215 // Rd = #-1 in getDuplexCandidateGroup()
4316 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrTimingClassLatency()
4319 /// getOperandLatency - Compute and return the use operand latency of a given
4339 if (Idx != -1) { in getOperandLatency()
4350 if (Idx != -1) { in getOperandLatency()
4369 // p -> NotP
4370 // NotP -> P
4399 return ~(-1U << (bits - 1)); in getMaxValue()
4401 return ~(-1U << bits); in getMaxValue()
4451 void HexagonInstrInfo::changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, in changeDuplexOpcode() argument
4453 int Opcode = -1; in changeDuplexOpcode()
4456 if (getDuplexCandidateGroup(*MII)) in changeDuplexOpcode()
4458 Opcode = getDuplexOpcode(*MII, ToBigInstrs); in changeDuplexOpcode()
4460 Opcode = getDuplexOpcode(*MII, ToBigInstrs); in changeDuplexOpcode()
4464 MII->setDesc(get(Opcode)); in changeDuplexOpcode()
4480 MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const { in translateInstrsForDup() argument
4481 MachineBasicBlock *MBB = MII->getParent(); in translateInstrsForDup()
4482 while ((MII != MBB->instr_end()) && MII->isInsideBundle()) { in translateInstrsForDup()
4483 changeDuplexOpcode(MII, ToBigInstrs); in translateInstrsForDup()
4484 ++MII; in translateInstrsForDup()
4519 return -1U << (bits - 1); in getMinValue()
4524 // Returns opcode of the non-extended equivalent instruction.
4527 // of the extended operand, if so return that as the non-extended form. in getNonExtOpcode()
4533 // Check addressing mode and retrieve non-ext equivalent instruction. in getNonExtOpcode()
4543 return -1; in getNonExtOpcode()
4546 return -1; in getNonExtOpcode()
4555 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop"); in getPredReg()
4598 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); in getSize()
4604 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?"); in getSize()
4629 return nonDbgMICount(BB->instr_begin(), BB->instr_end()); in nonDbgBBSize()
4634 assert(BundleHead->isBundle() && "Not a bundle header"); in nonDbgBundleSize()
4635 auto MII = BundleHead.getInstrIterator(); in nonDbgBundleSize() local
4637 return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator())); in nonDbgBundleSize()
4640 /// immediateExtend - Changes the instruction in place to one using an immediate
4662 int TargetPos = MI.getNumOperands() - 1; in invertAndChangeJumpTarget()
4665 while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB()) in invertAndChangeJumpTarget()
4666 --TargetPos; in invertAndChangeJumpTarget()
4681 DebugLoc DL = I->getDebugLoc(); in genAllInsnTimingClasses()
4688 << getName(NewMI->getOpcode()) in genAllInsnTimingClasses()
4689 << " Class: " << NewMI->getDesc().getSchedClass()); in genAllInsnTimingClasses()
4690 NewMI->eraseFromParent(); in genAllInsnTimingClasses()
4692 /* --- The code above is used to generate complete set of Hexagon Insn --- */ in genAllInsnTimingClasses()
4696 // p -> NotP
4697 // NotP -> P
4706 int PredRevOpcode = -1; in reversePrediction()
4723 assert(MIB->isBundle()); in setBundleNoShuf()
4724 MachineOperand &Operand = MIB->getOperand(0); in setBundleNoShuf()
4728 MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask)); in setBundleNoShuf()