232     MachineInstr *DefI = MRI->getVRegDef(Reg.R);  in processPredicateGPR()  local
233     DefI->eraseFromParent();  in processPredicateGPR()
254   MachineInstr *DefI = MRI->getVRegDef(Reg.R);  in getPredRegFor()  local
255   assert(DefI);  in getPredRegFor()
256   unsigned Opc = DefI->getOpcode();  in getPredRegFor()
258     assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse());  in getPredRegFor()
259     RegisterSubReg PR = DefI->getOperand(1);  in getPredRegFor()
265   MachineBasicBlock &B = *DefI->getParent();  in getPredRegFor()
266   DebugLoc DL = DefI->getDebugLoc();  in getPredRegFor()
272   if (isConvertibleToPredForm(DefI)) {  in getPredRegFor()
273     MachineBasicBlock::iterator DefIt = DefI;  in getPredRegFor()
328     const MachineInstr *DefI = MRI->getVRegDef(PR.R);  in isScalarPred()  local
329     if (!DefI)  in isScalarPred()
331     unsigned DefOpc = DefI->getOpcode();  in isScalarPred()
353         for (const MachineOperand &MO : DefI->operands())  in isScalarPred()