Lines Matching full:hexagon
65 #define DEBUG_TYPE "hexagon-pei"
67 // Hexagon stack frame layout as defined by the ABI:
151 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
152 cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
174 EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden,
187 static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),
190 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
239 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
240 "Hexagon call frame information", false, false)
251 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) in getMax32BitSubRegister()
270 static_assert(Hexagon::R1 > 0, in getMaxCalleeSavedReg()
293 case Hexagon::PS_alloca: in needsStackFrame()
294 case Hexagon::PS_aligna: in needsStackFrame()
347 return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r; in hasTailCall()
369 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: in isRestoreCall()
370 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC: in isRestoreCall()
371 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT: in isRestoreCall()
372 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC: in isRestoreCall()
373 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT: in isRestoreCall()
374 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC: in isRestoreCall()
375 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4: in isRestoreCall()
376 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC: in isRestoreCall()
443 BitVector CSR(Hexagon::NUM_TARGET_REGS); in findShrunkPrologEpilog()
622 if (MI.getOpcode() == Hexagon::PS_alloca) in insertPrologueInBlock()
626 assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca"); in insertPrologueInBlock()
643 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP) in insertPrologueInBlock()
674 LDOpc = Hexagon::L2_loadrb_io; in insertPrologueInBlock()
675 STOpc = Hexagon::S2_storerb_io; in insertPrologueInBlock()
678 LDOpc = Hexagon::L2_loadrh_io; in insertPrologueInBlock()
679 STOpc = Hexagon::S2_storerh_io; in insertPrologueInBlock()
682 LDOpc = Hexagon::L2_loadri_io; in insertPrologueInBlock()
683 STOpc = Hexagon::S2_storeri_io; in insertPrologueInBlock()
687 LDOpc = Hexagon::L2_loadrd_io; in insertPrologueInBlock()
688 STOpc = Hexagon::S2_storerd_io; in insertPrologueInBlock()
692 Register RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3 in insertPrologueInBlock()
693 : Hexagon::R6; in insertPrologueInBlock()
736 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_storeri_io)) in insertPrologueInBlock()
739 .addReg(Hexagon::R0 + j) in insertPrologueInBlock()
748 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP) in insertPrologueInBlock()
756 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk)) in insertPrologueInBlock()
760 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP) in insertPrologueInBlock()
781 // On Hexagon Linux, deallocate the stack for the register saved area. in insertEpilogueInBlock()
788 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP) in insertEpilogueInBlock()
799 if (RetOpc == Hexagon::EH_RETURN_JMPR) { in insertEpilogueInBlock()
800 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe)) in insertEpilogueInBlock()
801 .addDef(Hexagon::D15) in insertEpilogueInBlock()
802 .addReg(Hexagon::R30); in insertEpilogueInBlock()
803 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP) in insertEpilogueInBlock()
805 .addReg(Hexagon::R28); in insertEpilogueInBlock()
811 if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 || in insertEpilogueInBlock()
812 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC || in insertEpilogueInBlock()
813 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT || in insertEpilogueInBlock()
814 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) { in insertEpilogueInBlock()
834 if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 || in insertEpilogueInBlock()
835 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC || in insertEpilogueInBlock()
836 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT || in insertEpilogueInBlock()
837 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC || in insertEpilogueInBlock()
838 COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr) in insertEpilogueInBlock()
849 if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) { in insertEpilogueInBlock()
850 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe)) in insertEpilogueInBlock()
851 .addDef(Hexagon::D15) in insertEpilogueInBlock()
852 .addReg(Hexagon::R30); in insertEpilogueInBlock()
855 unsigned NewOpc = Hexagon::L4_return; in insertEpilogueInBlock()
857 .addDef(Hexagon::D15) in insertEpilogueInBlock()
858 .addReg(Hexagon::R30); in insertEpilogueInBlock()
873 (I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT && in insertEpilogueInBlock()
874 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC && in insertEpilogueInBlock()
875 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 && in insertEpilogueInBlock()
876 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC)) in insertEpilogueInBlock()
877 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe)) in insertEpilogueInBlock()
878 .addDef(Hexagon::D15) in insertEpilogueInBlock()
879 .addReg(Hexagon::R30); in insertEpilogueInBlock()
881 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP) in insertEpilogueInBlock()
908 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe)) in insertAllocframe()
916 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP) in insertAllocframe()
920 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe)) in insertAllocframe()
1006 if (I.getOpcode() == Hexagon::S2_allocframe) in findCFILocation()
1014 if (T->getOpcode() == Hexagon::S2_allocframe) in findCFILocation()
1077 Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2, in insertCFIInstructionsAt()
1078 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18, in insertCFIInstructionsAt()
1079 Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22, in insertCFIInstructionsAt()
1080 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26, in insertCFIInstructionsAt()
1081 Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9, in insertCFIInstructionsAt()
1082 Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, in insertCFIInstructionsAt()
1083 Hexagon::NoRegister in insertCFIInstructionsAt()
1088 for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) { in insertCFIInstructionsAt()
1115 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) { in insertCFIInstructionsAt()
1128 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt()
1129 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt()
1244 case Hexagon::R17: in getSpillFunctionFor()
1246 case Hexagon::R19: in getSpillFunctionFor()
1248 case Hexagon::R21: in getSpillFunctionFor()
1250 case Hexagon::R23: in getSpillFunctionFor()
1252 case Hexagon::R25: in getSpillFunctionFor()
1254 case Hexagon::R27: in getSpillFunctionFor()
1387 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC in insertCSRSpillsInBlock()
1388 : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT; in insertCSRSpillsInBlock()
1390 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC in insertCSRSpillsInBlock()
1391 : Hexagon::SAVE_REGISTERS_CALL_V4STK; in insertCSRSpillsInBlock()
1394 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC in insertCSRSpillsInBlock()
1395 : Hexagon::SAVE_REGISTERS_CALL_V4_EXT; in insertCSRSpillsInBlock()
1397 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC in insertCSRSpillsInBlock()
1398 : Hexagon::SAVE_REGISTERS_CALL_V4; in insertCSRSpillsInBlock()
1455 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC in insertCSRRestoresInBlock()
1456 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT; in insertCSRRestoresInBlock()
1458 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC in insertCSRRestoresInBlock()
1459 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4; in insertCSRRestoresInBlock()
1468 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC in insertCSRRestoresInBlock()
1469 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT; in insertCSRRestoresInBlock()
1471 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC in insertCSRRestoresInBlock()
1472 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4; in insertCSRRestoresInBlock()
1498 assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) && in eliminateCallFramePseudoInstr()
1562 BitVector SRegs(Hexagon::NUM_TARGET_REGS); in assignCalleeSavedSpillSlots()
1618 BitVector TmpSup(Hexagon::NUM_TARGET_REGS); in assignCalleeSavedSpillSlots()
1725 if (!Hexagon::ModRegsRegClass.contains(DstR) || in expandCopy()
1726 !Hexagon::ModRegsRegClass.contains(SrcR)) in expandCopy()
1729 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in expandCopy()
1754 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in expandStoreInt()
1755 unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr in expandStoreInt()
1756 : Hexagon::A2_tfrcrr; in expandStoreInt()
1761 BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io)) in expandStoreInt()
1785 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in expandLoadInt()
1786 BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR) in expandLoadInt()
1793 unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp in expandLoadInt()
1794 : Hexagon::A2_tfrrcr; in expandLoadInt()
1814 auto *RC = &Hexagon::HvxVRRegClass; in expandStoreVecPred()
1820 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in expandStoreVecPred()
1823 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0) in expandStoreVecPred()
1826 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1) in expandStoreVecPred()
1850 auto *RC = &Hexagon::HvxVRRegClass; in expandLoadVecPred()
1855 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in expandLoadVecPred()
1858 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0) in expandLoadVecPred()
1865 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR) in expandLoadVecPred()
1899 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2()
1900 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2()
1904 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandStoreVec2()
1905 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec2()
1911 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec2()
1912 : Hexagon::V6_vS32Ub_ai; in expandStoreVec2()
1922 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec2()
1923 : Hexagon::V6_vS32Ub_ai; in expandStoreVec2()
1947 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi); in expandLoadVec2()
1948 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); in expandLoadVec2()
1951 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandLoadVec2()
1952 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec2()
1957 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec2()
1958 : Hexagon::V6_vL32Ub_ai; in expandLoadVec2()
1965 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec2()
1966 : Hexagon::V6_vL32Ub_ai; in expandLoadVec2()
1991 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec()
1993 unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec()
1994 : Hexagon::V6_vS32Ub_ai; in expandStoreVec()
2019 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec()
2021 unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec()
2022 : Hexagon::V6_vL32Ub_ai; in expandLoadVec()
2050 case Hexagon::STriw_pred: in expandSpillMacros()
2051 case Hexagon::STriw_ctr: in expandSpillMacros()
2054 case Hexagon::LDriw_pred: in expandSpillMacros()
2055 case Hexagon::LDriw_ctr: in expandSpillMacros()
2058 case Hexagon::PS_vstorerq_ai: in expandSpillMacros()
2061 case Hexagon::PS_vloadrq_ai: in expandSpillMacros()
2064 case Hexagon::PS_vloadrw_ai: in expandSpillMacros()
2067 case Hexagon::PS_vstorerw_ai: in expandSpillMacros()
2104 SpillRCs.insert(&Hexagon::IntRegsRegClass); in determineCalleeSaves()
2114 case Hexagon::IntRegsRegClassID: in determineCalleeSaves()
2117 case Hexagon::HvxQRRegClassID: in determineCalleeSaves()
2468 CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth; in optimizeSpillSlots()
2470 CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth; in optimizeSpillSlots()
2513 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd) in expandAlloca()
2518 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP) in expandAlloca()
2524 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd) in expandAlloca()
2528 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP) in expandAlloca()
2539 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd) in expandAlloca()
2559 if (I.getOpcode() == Hexagon::PS_aligna) in getAlignaInstr()
2591 BitVector Regs(Hexagon::NUM_TARGET_REGS); in shouldInlineCSR()
2594 if (!Hexagon::DoubleRegsRegClass.contains(R)) in shouldInlineCSR()
2599 if (F != Hexagon::D8) in shouldInlineCSR()
2664 case Hexagon::S4_storeirit_io: in mayOverflowFrameOffset()
2665 case Hexagon::S4_storeirif_io: in mayOverflowFrameOffset()
2666 case Hexagon::S4_storeiri_io: in mayOverflowFrameOffset()
2669 case Hexagon::S4_storeirht_io: in mayOverflowFrameOffset()
2670 case Hexagon::S4_storeirhf_io: in mayOverflowFrameOffset()
2671 case Hexagon::S4_storeirh_io: in mayOverflowFrameOffset()
2674 case Hexagon::S4_storeirbt_io: in mayOverflowFrameOffset()
2675 case Hexagon::S4_storeirbf_io: in mayOverflowFrameOffset()
2676 case Hexagon::S4_storeirb_io: in mayOverflowFrameOffset()
2730 // A variable size object has size equal to 0. Since Hexagon sets in orderFrameObjects()