Lines Matching +full:dsr +full:- +full:override
1 //===- HexagonExpandCondsets.cpp ------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // It is meant to work post-SSA, but still on virtual registers. It was
40 // ... [intervening instructions, %0->vreg3] ...
71 // removed (in case it is an identity copy), some pre-existing def may
78 // of %1 will need to be updated to non-dead at some point.
122 #define DEBUG_TYPE "expand-condsets"
126 static cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit",
128 static cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit",
152 StringRef getPassName() const override { return "Hexagon Expand Condsets"; } in getPassName()
154 void getAnalysisUsage(AnalysisUsage &AU) const override { in getAnalysisUsage()
163 bool runOnMachineFunction(MachineFunction &MF) override;
255 INITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets",
260 INITIALIZE_PASS_END(HexagonExpandCondsets, "expand-condsets", in INITIALIZE_PASS_DEPENDENCY()
293 return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub) in getLaneMask()
294 : MRI->getMaxLaneMaskForVReg(Reg); in getLaneMask()
304 F->second |= Mask; in addRefToMap()
313 if (Mask & F->second) in isRefInMap()
319 auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void { in updateKillFlags()
321 MachineInstr *MI = LIS->getInstructionFromIndex(K); in updateKillFlags()
322 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in updateKillFlags()
323 MachineOperand &Op = MI->getOperand(i); in updateKillFlags()
325 MI->isRegTiedToDefOperand(i)) in updateKillFlags()
337 LiveInterval &LI = LIS->getInterval(Reg); in updateKillFlags()
339 if (!I->end.isRegister()) in updateKillFlags()
344 if (NextI != E && NextI->start.isRegister()) { in updateKillFlags()
345 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start); in updateKillFlags()
346 if (HII->isPredicated(*DefI)) in updateKillFlags()
351 auto EndsAtI = [I] (LiveInterval::SubRange &S) -> bool { in updateKillFlags()
352 LiveRange::iterator F = S.find(I->end); in updateKillFlags()
353 return F != S.end() && I->end == F->end; in updateKillFlags()
355 // Check if all subranges end at I->end. If so, make sure to kill in updateKillFlags()
359 KillAt(I->end, S.LaneMask); in updateKillFlags()
365 KillAt(I->end, MRI->getMaxLaneMaskForVReg(Reg)); in updateKillFlags()
375 // Return two booleans: { def-modifes-reg, def-covers-reg }. in updateDeadsInRange()
376 auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool> { in updateDeadsInRange()
379 Register DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange() local
382 LaneBitmask SLM = getLaneMask(DR, DSR); in updateDeadsInRange()
395 MachineBasicBlock *Dest) -> bool { in updateDeadsInRange()
397 if (D != Dest && MDT->dominates(D, Dest)) in updateDeadsInRange()
400 MachineBasicBlock *Entry = &Dest->getParent()->front(); in updateDeadsInRange()
401 SetVector<MachineBasicBlock*> Work(Dest->pred_begin(), Dest->pred_end()); in updateDeadsInRange()
408 for (auto *P : B->predecessors()) in updateDeadsInRange()
422 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); in updateDeadsInRange()
423 Defs.insert(DefI->getParent()); in updateDeadsInRange()
424 if (HII->isPredicated(*DefI)) in updateDeadsInRange()
429 LiveInterval &LI = LIS->getInterval(Reg); in updateDeadsInRange()
430 LI.computeSubRangeUndefs(Undefs, LM, *MRI, *LIS->getSlotIndexes()); in updateDeadsInRange()
433 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI); in updateDeadsInRange()
434 auto P = Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB), SI); in updateDeadsInRange()
440 // by the in-block extension. in updateDeadsInRange()
445 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI); in updateDeadsInRange()
446 if (BB->pred_empty()) in updateDeadsInRange()
463 LIS->extendToIndices(Range, ExtTo, Undefs); in updateDeadsInRange()
476 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); in updateDeadsInRange()
477 for (auto &Op : DefI->operands()) { in updateDeadsInRange()
493 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); in updateDeadsInRange()
494 if (!HII->isPredicated(*DefI)) in updateDeadsInRange()
500 for (unsigned i = 0, e = DefI->getNumOperands(); i != e; ++i) { in updateDeadsInRange()
501 MachineOperand &Op = DefI->getOperand(i); in updateDeadsInRange()
521 MachineFunction &MF = *DefI->getParent()->getParent(); in updateDeadsInRange()
524 DefI->tieOperands(DefIdx, DefI->getNumOperands()-1); in updateDeadsInRange()
530 LiveInterval &LI = LIS->getInterval(Reg); in updateDeadFlags()
534 LIS->shrinkToUses(S, Reg); in updateDeadFlags()
537 LIS->constructMainRangeFromSubranges(LI); in updateDeadFlags()
539 updateDeadsInRange(Reg, MRI->getMaxLaneMaskForVReg(Reg), LI); in updateDeadFlags()
544 LIS->removeInterval(Reg); in recalculateLiveInterval()
545 LIS->createAndComputeVirtRegInterval(Reg); in recalculateLiveInterval()
549 LIS->RemoveMachineInstrFromMaps(MI); in removeInstr()
562 assert(MRI->isReserved(R)); in updateLiveness()
568 MRI->clearKillFlags(R); in updateLiveness()
575 LIS->getInterval(R).verify(); in updateLiveness()
585 LiveInterval &LI = LIS->getInterval(R); in distributeLiveIntervals()
591 const TargetRegisterClass *RC = MRI->getRegClass(LI.reg()); in distributeLiveIntervals()
593 Register NewR = MRI->createVirtualRegister(RC); in distributeLiveIntervals()
594 NewLIs.push_back(&LIS->createEmptyInterval(NewR)); in distributeLiveIntervals()
608 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg); in getCondTfrOpcode()
609 assert(VC->begin() != VC->end() && "Empty register class"); in getCondTfrOpcode()
610 PhysR = *VC->begin(); in getCondTfrOpcode()
614 MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode()
615 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); in getCondTfrOpcode()
616 switch (TRI->getRegSizeInBits(*RC)) { in getCondTfrOpcode()
649 MachineBasicBlock &B = *At->getParent(); in genCondTfrFor()
650 const DebugLoc &DL = MI->getDebugLoc(); in genCondTfrFor()
667 MIB = BuildMI(B, At, DL, HII->get(Opc)) in genCondTfrFor()
672 MIB = BuildMI(B, At, DL, HII->get(Opc)) in genCondTfrFor()
696 Register DR = MD.getReg(), DSR = MD.getSubReg(); in split() local
700 auto updateRegs = [&UpdRegs] (const MachineInstr &MI) -> void { in split()
717 MI.setDesc(HII->get(TargetOpcode::COPY)); in split()
720 MI.removeOperand(MI.getNumOperands()-1); in split()
721 MachineFunction &MF = *MI.getParent()->getParent(); in split()
731 genCondTfrFor(ST, At, DR, DSR, MP, true, ReadUndef, false); in split()
733 genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true); in split()
734 LIS->InsertMachineInstrInMaps(*TfrT); in split()
735 LIS->InsertMachineInstrInMaps(*TfrF); in split()
745 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
747 if (MI->hasUnmodeledSideEffects() || MI->mayStore()) in isPredicable()
749 // Reject instructions with multiple defs (e.g. post-increment loads). in isPredicable()
751 for (auto &Op : MI->operands()) { in isPredicable()
758 for (auto &Mo : MI->memoperands()) { in isPredicable()
759 if (Mo->isVolatile() || Mo->isAtomic()) in isPredicable()
770 MachineBasicBlock &B = *UseIt->getParent(); in getReachingDefForPred()
777 --I; in getReachingDefForPred()
781 if (PredValid && HII->isPredicated(*MI)) { in getReachingDefForPred()
782 if (MI->readsRegister(PredR, /*TRI=*/nullptr) && in getReachingDefForPred()
783 (Cond != HII->isPredicatedTrue(*MI))) in getReachingDefForPred()
789 for (auto &Op : MI->operands()) { in getReachingDefForPred()
814 /// whose side-effects (in terms of register defs and uses) are expressed in
849 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI)) in canMoveMemTo()
894 DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction. in predicateAt()
896 unsigned PredOpc = HII->getCondOpcode(Opc, !Cond); in predicateAt()
897 MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc)); in predicateAt()
920 NewI->clearKillInfo(); in predicateAt()
921 LIS->InsertMachineInstrInMaps(*NewI); in predicateAt()
923 for (auto &Op : NewI->operands()) { in predicateAt()
939 if (!HII->isPredicated(MI)) in renameInRange()
942 (Cond != HII->isPredicatedTrue(MI))) in renameInRange()
961 // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi). in predicate()
965 LLVM_DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false") in predicate()
978 if (MD.getSubReg() && !MRI->shouldTrackSubRegLiveness(MD.getReg())) in predicate()
991 // Map: reg -> bitmask of subregs in predicate()
1012 if (PredValid && HII->isPredicated(MI) && in predicate()
1014 Exec = (Cond == HII->isPredicatedTrue(MI)) ? Exec_Then : Exec_Else; in predicate()
1023 // registers ters no longer have subregisters---their super- and in predicate()
1032 assert(RR.Sub && "Expecting a subregister on <def,read-undef>"); in predicate()
1033 // If this is a <def,read-undef>, then it invalidates the non-written in predicate()
1047 // If the register-in-the-middle (RT) is used or redefined between in predicate()
1068 if (DefI->mayLoadOrStore()) { in predicate()
1121 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg); in isIntReg()
1154 if (MRI->isLiveIn(R1.Reg)) in coalesceRegisters()
1156 if (MRI->isLiveIn(R2.Reg)) in coalesceRegisters()
1159 LiveInterval &L1 = LIS->getInterval(R1.Reg); in coalesceRegisters()
1160 LiveInterval &L2 = LIS->getInterval(R2.Reg); in coalesceRegisters()
1182 MRI->replaceRegWith(R2.Reg, R1.Reg); in coalesceRegisters()
1191 NewVN = L1.getNextValue(I.valno->def, LIS->getVNInfoAllocator()); in coalesceRegisters()
1194 NewVN = F->second; in coalesceRegisters()
1200 LIS->removeInterval(R2.Reg); in coalesceRegisters()
1217 MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3); in coalesceSegments()
1225 RegisterRef RD = CI->getOperand(0); in coalesceSegments()
1226 RegisterRef RP = CI->getOperand(1); in coalesceSegments()
1227 MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3); in coalesceSegments()
1250 if (!RDef || !HII->isPredicable(*RDef)) { in coalesceSegments()
1261 if (!RDef || !HII->isPredicable(*RDef)) { in coalesceSegments()
1284 LLVM_DEBUG(LIS->print(dbgs() << "Before expand-condsets\n")); in runOnMachineFunction()
1302 // at this moment (when expand-condsets runs), there are no kill flags in runOnMachineFunction()
1308 for (MachineOperand &Op : MI->operands()) { in runOnMachineFunction()
1316 LLVM_DEBUG(LIS->print(dbgs() << "After coalescing\n")); in runOnMachineFunction()
1332 LLVM_DEBUG(LIS->print(dbgs() << "After splitting\n")); in runOnMachineFunction()
1336 // Walk over all the instructions again, so we may catch pre-existing in runOnMachineFunction()
1340 LLVM_DEBUG(LIS->print(dbgs() << "After predicating\n")); in runOnMachineFunction()
1350 LIS->print(dbgs() << "After expand-condsets\n"); in runOnMachineFunction()
1356 //===----------------------------------------------------------------------===//
1358 //===----------------------------------------------------------------------===//