Lines Matching refs:R1
363 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2,
365 bool evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1, const APInt &A2,
367 bool evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1, uint64_t Props2,
376 bool evaluateCOPY(const RegisterSubReg &R1, const CellMap &Inputs,
380 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
382 bool evaluateANDri(const RegisterSubReg &R1, const APInt &A2,
385 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
387 bool evaluateORri(const RegisterSubReg &R1, const APInt &A2,
390 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
392 bool evaluateXORri(const RegisterSubReg &R1, const APInt &A2,
397 bool evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
401 bool evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
407 bool evaluateCLBr(const RegisterSubReg &R1, bool Zeros, bool Ones,
410 bool evaluateCTBr(const RegisterSubReg &R1, bool Zeros, bool Ones,
415 bool evaluateEXTRACTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
421 bool evaluateSplatr(const RegisterSubReg &R1, unsigned Bits, unsigned Count,
1105 bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1,
1107 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
1109 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
1123 return evaluateCMPrp(Cmp, R1, Prop2, Inputs, Result);
1131 evaluateCMPri(Cmp, R1, A, Inputs, Res);
1144 bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1,
1146 assert(Inputs.has(R1.Reg));
1148 if (!getCell(R1, Inputs, LS))
1171 bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1,
1173 assert(Inputs.has(R1.Reg));
1175 if (!getCell(R1, Inputs, LS))
1364 bool MachineConstEvaluator::evaluateCOPY(const RegisterSubReg &R1,
1366 return getCell(R1, Inputs, Result);
1369 bool MachineConstEvaluator::evaluateANDrr(const RegisterSubReg &R1,
1371 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
1380 return evaluateANDrr(R2, R1, Inputs, Result);
1392 evaluateANDri(R1, A, Inputs, RC);
1400 bool MachineConstEvaluator::evaluateANDri(const RegisterSubReg &R1,
1402 assert(Inputs.has(R1.Reg));
1404 return getCell(R1, Inputs, Result);
1413 if (!getCell(R1, Inputs, LS1))
1436 bool MachineConstEvaluator::evaluateORrr(const RegisterSubReg &R1,
1438 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
1447 return evaluateORrr(R2, R1, Inputs, Result);
1459 evaluateORri(R1, A, Inputs, RC);
1467 bool MachineConstEvaluator::evaluateORri(const RegisterSubReg &R1,
1469 assert(Inputs.has(R1.Reg));
1471 return getCell(R1, Inputs, Result);
1480 if (!getCell(R1, Inputs, LS1))
1503 bool MachineConstEvaluator::evaluateXORrr(const RegisterSubReg &R1,
1505 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
1507 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
1524 evaluateXORri(R1, A, Inputs, RC);
1532 bool MachineConstEvaluator::evaluateXORri(const RegisterSubReg &R1,
1534 assert(Inputs.has(R1.Reg));
1536 if (!getCell(R1, Inputs, LS1))
1565 bool MachineConstEvaluator::evaluateZEXTr(const RegisterSubReg &R1, unsigned Width,
1567 assert(Inputs.has(R1.Reg));
1569 if (!getCell(R1, Inputs, LS1))
1596 bool MachineConstEvaluator::evaluateSEXTr(const RegisterSubReg &R1, unsigned Width,
1598 assert(Inputs.has(R1.Reg));
1600 if (!getCell(R1, Inputs, LS1))
1661 bool MachineConstEvaluator::evaluateCLBr(const RegisterSubReg &R1, bool Zeros,
1663 assert(Inputs.has(R1.Reg));
1665 if (!getCell(R1, Inputs, LS1))
1696 bool MachineConstEvaluator::evaluateCTBr(const RegisterSubReg &R1, bool Zeros,
1698 assert(Inputs.has(R1.Reg));
1700 if (!getCell(R1, Inputs, LS1))
1731 bool MachineConstEvaluator::evaluateEXTRACTr(const RegisterSubReg &R1,
1734 assert(Inputs.has(R1.Reg));
1737 if (!getCell(R1, Inputs, LS1))
1789 bool MachineConstEvaluator::evaluateSplatr(const RegisterSubReg &R1,
1792 assert(Inputs.has(R1.Reg));
1794 if (!getCell(R1, Inputs, LS1))
2091 RegisterSubReg R1(MI.getOperand(1));
2092 assert(Inputs.has(R1.Reg));
2094 bool Eval = evaluateCTBr(R1, !Ones, Ones, Inputs, T);
2123 RegisterSubReg R1(MI.getOperand(1));
2124 assert(Inputs.has(R1.Reg));
2126 bool Eval = evaluateCLBr(R1, !OnlyOnes, !OnlyZeros, Inputs, T);
2151 RegisterSubReg R1(MI.getOperand(1));
2152 unsigned BW = getRegBitWidth(R1.Reg);
2168 bool Eval = evaluateEXTRACTr(R1, BW, Bits, Offset, Signed, Inputs, RC);
2604 RegisterSubReg R1(Src1);
2607 return evaluateCMPrr(Cmp, R1, R2, Inputs, Result);
2610 return evaluateCMPri(Cmp, R1, A2, Inputs, Result);
2634 RegisterSubReg R1(Src1);
2642 Eval = evaluateANDrr(R1, RegisterSubReg(Src2), Inputs, RC);
2648 Eval = evaluateANDri(R1, A, Inputs, RC);
2653 Eval = evaluateORrr(R1, RegisterSubReg(Src2), Inputs, RC);
2659 Eval = evaluateORri(R1, A, Inputs, RC);
2664 Eval = evaluateXORrr(R1, RegisterSubReg(Src2), Inputs, RC);
2719 // Dst0 = ext R1
2720 RegisterSubReg R1(MI.getOperand(1));
2721 assert(Inputs.has(R1.Reg));
2753 bool Eval = Signed ? evaluateSEXTr(R1, BW, Bits, Inputs, RC)
2754 : evaluateZEXTr(R1, BW, Bits, Inputs, RC);
2763 // DefR = op R1
2765 RegisterSubReg R1(MI.getOperand(1));
2766 assert(Inputs.has(R1.Reg));
2774 Eval = evaluateSplatr(R1, 8, 4, Inputs, RC);
2778 Eval = evaluateSplatr(R1, 16, 4, Inputs, RC);
2988 // DefR == R1 (tied operands).
2990 RegisterSubReg R1(Acc);
2991 unsigned NewR = R1.Reg;
2992 if (R1.SubReg) {
2997 .addReg(R1.Reg, getRegState(Acc), R1.SubReg);
3037 RegisterSubReg R1(MI.getOperand(1));
3039 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
3043 if (getCell(R1, Inputs, LS1) && LS1.isSingle()) {
3073 RegisterSubReg R1(MI.getOperand(1));
3075 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
3081 if (getCell(R1, Inputs, LS1) && (LS1.properties() & P::Zero))