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1 //===- HexagonConstPropagation.cpp ----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
54 // value is known (proven) to have this property. Not all combinations
102 // Lattice cell, based on that was described in the W-Z paper on constant
107 // could be folded if all the values in the cell associated with X are
201 // Mapping: vreg -> cell
221 // All non-virtual registers are considered "bottom".
233 return F->second;
289 // as well as some helper functions that are target-independent.
298 // - A set of three "evaluate" functions. Each returns "true" if the
301 // compute the set of output values "Outputs". An example of when
307 // If the branch can fall-through, add null (0) to the list of
309 // - A function "rewrite", that given the cell map after propagation,
314 CellMap &Outputs) = 0;
333 L = 0x04, // Less-than property.
334 G = 0x08, // Greater-than property.
432 if (CI->isZero())
435 if (CI->isNegative())
442 uint32_t Props = CF->isNegative() ? (NegOrZero|NonZero)
444 if (CF->isZero())
447 if (CF->isNaN())
449 const APFloat &Val = CF->getValueAPF();
511 C->print(os);
589 // Add a property to the cell. This will force the cell to become a property-
623 dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n';
629 unsigned MBN = MB->getNumber();
638 // If the def has a sub-register, set the corresponding cell to "bottom".
653 unsigned PBN = PB->getNumber();
655 LLVM_DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->"
687 CellMap Outputs;
688 bool Eval = MCE.evaluate(MI, Cells, Outputs);
691 dbgs() << " outputs:";
692 for (auto &I : Outputs)
698 // Update outputs. If the value was not computed, set all the
708 // If the evaluation failed, set cells for all output registers to bottom.
714 // Find the corresponding cell in the computed outputs.
716 if (!Outputs.has(DefR.Reg))
719 Changed = RC.meet(Outputs.get(DefR.Reg));
729 // can fall through. Add all the possible targets to the flow work queue,
730 // including the potential fall-through to the layout-successor block.
759 // Need to add all CFG successors that lead to EH landing pads.
763 if (SB->isEHPad())
775 // set of all successors of the block from the CFG.
776 // If the evaluation succeeded for all visited branches, then if the
780 LLVM_DEBUG(dbgs() << " failed to evaluate a branch...adding all CFG "
787 unsigned TBN = TB->getNumber();
788 LLVM_DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> "
797 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
798 // Do not process non-executable instructions. They can become exceutable
799 // later (via a flow-edge in the work queue). In such case, the instruc-
816 MachineBasicBlock::const_iterator FirstBr = MB->end();
828 MachineBasicBlock::const_iterator End = MB->end();
844 // If the last branch could fall-through, add block's layout successor.
846 MachineFunction::const_iterator BI = MB->getIterator();
848 if (NextI != MB->getParent()->end())
852 // Add all the EH landing pads.
853 for (const MachineBasicBlock *SB : MB->successors())
854 if (SB->isEHPad())
863 From->removeSuccessor(To);
864 // Remove all corresponding PHI operands in the To block.
865 for (MachineInstr &PN : To->phis()) {
867 int N = PN.getNumOperands() - 2;
873 N -= 2;
880 unsigned EntryNum = Entry->getNumber();
891 << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->"
900 // - visit all PHI nodes,
901 // - visit all non-branch instructions,
902 // - visit block branches.
903 MachineBasicBlock::const_iterator It = SB->begin(), End = SB->end();
906 while (It != End && It->isPHI()) {
912 // If the successor block just became executable, visit all instructions.
914 // non-debug instruction to see if it is executable.
915 while (It != End && It->isDebugInstr())
917 assert(It == End || !It->isPHI());
921 // For now, scan all non-branch instructions. Branches require different
923 while (It != End && !It->isBranch()) {
924 if (!It->isDebugInstr()) {
932 // processing regular (non-branch) instructions, because there can
938 // If the block didn't have a branch, add all successor edges to the
940 unsigned SBN = SB->getNumber();
941 for (const MachineBasicBlock *SSB : SB->successors())
942 FlowQ.push(CFGEdge(SBN, SSB->getNumber()));
953 unsigned SN = SB->getNumber();
955 dbgs() << " " << printMBBReference(B) << " -> "
964 // Rewrite all instructions based on the collected cell information.
966 // Traverse the instructions in a post-order, so that rewriting an
967 // instruction can make changes "downstream" in terms of control-flow
977 // Collect the post-order-traversal block ordering. The subsequent
982 if (!B->empty())
1004 // The rewriting could rewrite PHI nodes to non-PHI nodes, causing
1005 // regular instructions to appear in between PHI nodes. Bring all
1007 for (auto I = B->begin(), E = B->end(); I != E; ++I) {
1008 if (I->isPHI())
1013 if (P->isPHI())
1019 B->splice(I, B, P);
1021 --I;
1026 for (MachineBasicBlock *SB : B->successors()) {
1035 // This could legitimately happen in blocks that have non-returning
1036 // calls---we would think that the execution can continue, but the
1040 // Need to do some final post-processing.
1053 // This is the constant propagation algorithm as described by Wegman-Zadeck.
1076 // --------------------------------------------------------------------
1097 Val = CI->getValue();
1327 // or a known non-zero.
1375 // with the non-bottom argument passed as the immediate. This is to
1403 if (A2 == -1)
1442 // with the non-bottom argument passed as the immediate. This is to
1443 // catch cases of ORing with -1.
1472 if (A2 == -1) {
1642 // Shift left to lose all bits except lower "Bits" bits, then shift
1645 V = (V << (64-Bits)) >> (64-Bits);
1648 // V is a 64-bit sign-extended value. Convert it to APInt of desired
1774 V <<= (64-Bits-Offset);
1776 V >>= (64-Bits);
1778 V = static_cast<uint64_t>(V) >> (64-Bits);
1783 Result = A1.shl(BW-Bits-Offset).ashr(BW-Bits);
1785 Result = A1.shl(BW-Bits-Offset).lshr(BW-Bits);
1828 // ----------------------------------------------------------------------
1829 // Hexagon-specific code.
1845 CellMap &Outputs) override;
1864 CellMap &Outputs);
1865 // This is suitable to be called for compare-and-jump instructions.
1869 CellMap &Outputs);
1871 CellMap &Outputs);
1873 CellMap &Outputs);
1875 CellMap &Outputs);
1877 CellMap &Outputs);
1914 INITIALIZE_PASS(HexagonConstPropagation, "hexagon-constp",
1925 const CellMap &Inputs, CellMap &Outputs) {
1946 Outputs.update(DefR.Reg, RC);
1952 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg);
1968 Outputs.update(DefR.Reg, RC);
1972 bool Eval = evaluateHexCompare(MI, Inputs, Outputs);
1987 // Do this check for all instructions for safety.
1997 LatticeCell RC = Outputs.get(DefR.Reg);
1999 Outputs.update(DefR.Reg, RC);
2006 LatticeCell RC = Outputs.get(DefR.Reg);
2011 Outputs.update(DefR.Reg, RC);
2024 bool Eval = evaluateHexLogical(MI, Inputs, Outputs);
2040 LatticeCell RC = Outputs.get(DefR.Reg);
2042 Outputs.update(DefR.Reg, RC);
2052 LatticeCell RC = Outputs.get(DefR.Reg);
2056 Outputs.update(DefR.Reg, RC);
2065 bool Eval = evaluateHexCondMove(MI, Inputs, Outputs);
2077 bool Eval = evaluateHexExt(MI, Inputs, Outputs);
2097 // All of these instructions return a 32-bit value. The evaluate
2101 LatticeCell RC = Outputs.get(DefR.Reg);
2108 Outputs.update(DefR.Reg, RC);
2129 // All of these instructions return a 32-bit value. The evaluate
2133 LatticeCell RC = Outputs.get(DefR.Reg);
2140 Outputs.update(DefR.Reg, RC);
2155 LatticeCell RC = Outputs.get(DefR.Reg);
2165 Bits = BW-Offset;
2171 Outputs.update(DefR.Reg, RC);
2186 bool Eval = evaluateHexVector1(MI, Inputs, Outputs);
2208 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg);
2262 // all the branches in a basic block at once, so we cannot use it.
2285 // If the branch is of unknown type, assume that all successors are
2350 // If not all defs have been rewritten (i.e. the instruction defines
2351 // a register that is not compile-time constant), then try to rewrite
2360 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
2553 const CellMap &Inputs, CellMap &Outputs) {
2582 // Only create a zero/non-zero cell. At this time there isn't really
2585 LatticeCell L = Outputs.get(DefR.Reg);
2589 Outputs.update(DefR.Reg, L);
2628 const CellMap &Inputs, CellMap &Outputs) {
2669 Outputs.update(DefR.Reg, RC);
2675 const CellMap &Inputs, CellMap &Outputs) {
2693 LatticeCell RC = Outputs.get(DefR.Reg);
2701 Outputs.update(DefR.Reg, RC);
2711 Outputs.update(DefR.Reg, RC);
2718 const CellMap &Inputs, CellMap &Outputs) {
2752 LatticeCell RC = Outputs.get(DefR.Reg);
2757 Outputs.update(DefR.Reg, RC);
2762 const CellMap &Inputs, CellMap &Outputs) {
2767 LatticeCell RC = Outputs.get(DefR.Reg);
2786 Outputs.update(DefR.Reg, RC);
2795 // LLVM_DEBUG({...}) gets confused with all this code as an argument.
2832 // Avoid generating TFRIs for register transfers---this will keep the
2837 MachineFunction *MF = MI.getParent()->getParent();
2838 auto &HST = MF->getSubtarget<HexagonSubtarget>();
2840 // Collect all virtual register-def operands.
2862 // and replace all uses of the defined register with NewR.
2867 const TargetRegisterClass *RC = MRI->getRegClass(R);
2871 // If this a zero/non-zero cell, we can fold a definition
2884 Register NewR = MRI->createVirtualRegister(PredRC);
2906 Register NewR = MRI->createVirtualRegister(NewRC);
2926 } else if (MF->getFunction().hasOptSize() || !HST.isTinyCore()) {
2946 MachineFunction &MF = *MI.getParent()->getParent();
2971 // or DefR -= mpyi(R, #imm).
2980 // to replace one argument---whichever happens to be a single constant.
2994 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
2995 NewR = MRI->createVirtualRegister(RC);
3000 MRI->clearKillFlags(NewR);
3022 V = -V;
3023 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3024 Register NewR = MRI->createVirtualRegister(RC);
3042 // Check if any of the operands is -1 (i.e. all bits set).
3060 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3061 NewR = MRI->createVirtualRegister(RC);
3066 MRI->clearKillFlags(NewR);
3092 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3093 NewR = MRI->createVirtualRegister(RC);
3098 MRI->clearKillFlags(NewR);
3105 // clear all the kill flags of this new instruction.
3106 for (MachineOperand &MO : NewMI->operands())
3129 llvm::make_early_inc_range(MRI->use_operands(FromReg)))
3153 // MIB.addMBB needs non-const pointer.
3158 // erased as "non-executable". We can't mark any new instructions
3167 // This ensures that all implicit operands (e.g. implicit-def %r31, etc)
3169 for (auto &Op : NI->operands())
3171 NI->eraseFromParent();