Lines Matching +full:ls +full:- +full:bits
1 //===- HexagonConstPropagation.cpp ----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
55 // of bits make sense, for example Zero and NonZero are mutually exclusive,
102 // Lattice cell, based on that was described in the W-Z paper on constant
201 // Mapping: vreg -> cell
221 // All non-virtual registers are considered "bottom".
233 return F->second;
289 // as well as some helper functions that are target-independent.
298 // - A set of three "evaluate" functions. Each returns "true" if the
307 // If the branch can fall-through, add null (0) to the list of
309 // - A function "rewrite", that given the cell map after propagation,
333 L = 0x04, // Less-than property.
334 G = 0x08, // Greater-than property.
397 bool evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
399 bool evaluateZEXTi(const APInt &A1, unsigned Width, unsigned Bits,
401 bool evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
403 bool evaluateSEXTi(const APInt &A1, unsigned Width, unsigned Bits,
406 // Leading/trailing bits.
415 bool evaluateEXTRACTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
418 bool evaluateEXTRACTi(const APInt &A1, unsigned Bits, unsigned Offset,
421 bool evaluateSplatr(const RegisterSubReg &R1, unsigned Bits, unsigned Count,
423 bool evaluateSplati(const APInt &A1, unsigned Bits, unsigned Count,
432 if (CI->isZero())
435 if (CI->isNegative())
442 uint32_t Props = CF->isNegative() ? (NegOrZero|NonZero)
444 if (CF->isZero())
447 if (CF->isNaN())
449 const APFloat &Val = CF->getValueAPF();
511 C->print(os);
589 // Add a property to the cell. This will force the cell to become a property-
623 dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n';
629 unsigned MBN = MB->getNumber();
638 // If the def has a sub-register, set the corresponding cell to "bottom".
653 unsigned PBN = PB->getNumber();
655 LLVM_DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->"
730 // including the potential fall-through to the layout-successor block.
763 if (SB->isEHPad())
787 unsigned TBN = TB->getNumber();
788 LLVM_DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> "
797 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
798 // Do not process non-executable instructions. They can become exceutable
799 // later (via a flow-edge in the work queue). In such case, the instruc-
816 MachineBasicBlock::const_iterator FirstBr = MB->end();
828 MachineBasicBlock::const_iterator End = MB->end();
844 // If the last branch could fall-through, add block's layout successor.
846 MachineFunction::const_iterator BI = MB->getIterator();
848 if (NextI != MB->getParent()->end())
853 for (const MachineBasicBlock *SB : MB->successors())
854 if (SB->isEHPad())
863 From->removeSuccessor(To);
865 for (MachineInstr &PN : To->phis()) {
867 int N = PN.getNumOperands() - 2;
873 N -= 2;
880 unsigned EntryNum = Entry->getNumber();
891 << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->"
900 // - visit all PHI nodes,
901 // - visit all non-branch instructions,
902 // - visit block branches.
903 MachineBasicBlock::const_iterator It = SB->begin(), End = SB->end();
906 while (It != End && It->isPHI()) {
914 // non-debug instruction to see if it is executable.
915 while (It != End && It->isDebugInstr())
917 assert(It == End || !It->isPHI());
921 // For now, scan all non-branch instructions. Branches require different
923 while (It != End && !It->isBranch()) {
924 if (!It->isDebugInstr()) {
932 // processing regular (non-branch) instructions, because there can
940 unsigned SBN = SB->getNumber();
941 for (const MachineBasicBlock *SSB : SB->successors())
942 FlowQ.push(CFGEdge(SBN, SSB->getNumber()));
953 unsigned SN = SB->getNumber();
955 dbgs() << " " << printMBBReference(B) << " -> "
966 // Traverse the instructions in a post-order, so that rewriting an
967 // instruction can make changes "downstream" in terms of control-flow
977 // Collect the post-order-traversal block ordering. The subsequent
982 if (!B->empty())
1004 // The rewriting could rewrite PHI nodes to non-PHI nodes, causing
1007 for (auto I = B->begin(), E = B->end(); I != E; ++I) {
1008 if (I->isPHI())
1013 if (P->isPHI())
1019 B->splice(I, B, P);
1021 --I;
1026 for (MachineBasicBlock *SB : B->successors()) {
1035 // This could legitimately happen in blocks that have non-returning
1036 // calls---we would think that the execution can continue, but the
1040 // Need to do some final post-processing.
1053 // This is the constant propagation algorithm as described by Wegman-Zadeck.
1076 // --------------------------------------------------------------------
1097 Val = CI->getValue();
1147 LatticeCell LS;
1148 if (!getCell(R1, Inputs, LS))
1150 if (LS.isProperty())
1151 return evaluateCMPpi(Cmp, LS.properties(), A2, Result);
1155 for (unsigned i = 0; i < LS.size(); ++i) {
1157 bool Computed = constToInt(LS.Values[i], A) &&
1174 LatticeCell LS;
1175 if (!getCell(R1, Inputs, LS))
1177 if (LS.isProperty())
1178 return evaluateCMPpp(Cmp, LS.properties(), Props2, Result);
1183 for (unsigned i = 0; i < LS.size(); ++i) {
1185 bool Computed = constToInt(LS.Values[i], A) &&
1327 // or a known non-zero.
1375 // with the non-bottom argument passed as the immediate. This is to
1403 if (A2 == -1)
1442 // with the non-bottom argument passed as the immediate. This is to
1443 // catch cases of ORing with -1.
1472 if (A2 == -1) {
1566 unsigned Bits, const CellMap &Inputs, LatticeCell &Result) {
1577 evaluateZEXTi(A, Width, Bits, XA);
1587 unsigned Bits, APInt &Result) {
1590 assert(Width >= Bits && BW >= Bits);
1591 APInt Mask = APInt::getLowBitsSet(Width, Bits);
1597 unsigned Bits, const CellMap &Inputs, LatticeCell &Result) {
1608 evaluateSEXTi(A, Width, Bits, XA);
1618 unsigned Bits, APInt &Result) {
1620 assert(Width >= Bits && BW >= Bits);
1622 // Sign extension of 0 bits generates 0 as a result. This is consistent
1624 if (Bits == 0) {
1629 if (BW <= 64 && Bits != 0) {
1631 switch (Bits) {
1642 // Shift left to lose all bits except lower "Bits" bits, then shift
1645 V = (V << (64-Bits)) >> (64-Bits);
1648 // V is a 64-bit sign-extended value. Convert it to APInt of desired
1654 if (Bits < BW)
1655 Result = A1.trunc(Bits).sext(Width);
1656 else // Bits == BW
1732 unsigned Width, unsigned Bits, unsigned Offset, bool Signed,
1735 assert(Bits+Offset <= Width);
1754 evaluateEXTRACTi(A, Bits, Offset, Signed, CA);
1763 bool MachineConstEvaluator::evaluateEXTRACTi(const APInt &A1, unsigned Bits,
1766 assert(Bits+Offset <= BW);
1767 // Extracting 0 bits generates 0 as a result (as indicated by the HW people).
1768 if (Bits == 0) {
1774 V <<= (64-Bits-Offset);
1776 V >>= (64-Bits);
1778 V = static_cast<uint64_t>(V) >> (64-Bits);
1783 Result = A1.shl(BW-Bits-Offset).ashr(BW-Bits);
1785 Result = A1.shl(BW-Bits-Offset).lshr(BW-Bits);
1790 unsigned Bits, unsigned Count, const CellMap &Inputs,
1802 evaluateSplati(A, Bits, Count, SA);
1811 bool MachineConstEvaluator::evaluateSplati(const APInt &A1, unsigned Bits,
1814 unsigned BW = A1.getBitWidth(), SW = Count*Bits;
1815 APInt LoBits = (Bits < BW) ? A1.trunc(Bits) : A1.zext(Bits);
1821 Res <<= Bits;
1828 // ----------------------------------------------------------------------
1829 // Hexagon-specific code.
1865 // This is suitable to be called for compare-and-jump instructions.
1914 INITIALIZE_PASS(HexagonConstPropagation, "hexagon-constp",
1952 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg);
2097 // All of these instructions return a 32-bit value. The evaluate
2129 // All of these instructions return a 32-bit value. The evaluate
2153 unsigned Bits = MI.getOperand(2).getImm();
2161 if (Offset+Bits > BW) {
2163 // the extra bits are treated as 0s. To emulate this behavior, reduce
2164 // the number of requested bits, and make the extract unsigned.
2165 Bits = BW-Offset;
2168 bool Eval = evaluateEXTRACTr(R1, BW, Bits, Offset, Signed, Inputs, RC);
2208 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg);
2351 // a register that is not compile-time constant), then try to rewrite
2360 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
2582 // Only create a zero/non-zero cell. At this time there isn't really
2679 LatticeCell LS;
2680 if (!getCell(CR, Inputs, LS))
2682 uint32_t Ps = LS.properties();
2724 unsigned Bits;
2728 Bits = 8;
2732 Bits = 16;
2735 Bits = 32;
2753 bool Eval = Signed ? evaluateSEXTr(R1, BW, Bits, Inputs, RC)
2754 : evaluateZEXTr(R1, BW, Bits, Inputs, RC);
2832 // Avoid generating TFRIs for register transfers---this will keep the
2837 MachineFunction *MF = MI.getParent()->getParent();
2838 auto &HST = MF->getSubtarget<HexagonSubtarget>();
2840 // Collect all virtual register-def operands.
2867 const TargetRegisterClass *RC = MRI->getRegClass(R);
2871 // If this a zero/non-zero cell, we can fold a definition
2884 Register NewR = MRI->createVirtualRegister(PredRC);
2906 Register NewR = MRI->createVirtualRegister(NewRC);
2926 } else if (MF->getFunction().hasOptSize() || !HST.isTinyCore()) {
2946 MachineFunction &MF = *MI.getParent()->getParent();
2971 // or DefR -= mpyi(R, #imm).
2980 // to replace one argument---whichever happens to be a single constant.
2994 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
2995 NewR = MRI->createVirtualRegister(RC);
3000 MRI->clearKillFlags(NewR);
3022 V = -V;
3023 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3024 Register NewR = MRI->createVirtualRegister(RC);
3042 // Check if any of the operands is -1 (i.e. all bits set).
3060 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3061 NewR = MRI->createVirtualRegister(RC);
3066 MRI->clearKillFlags(NewR);
3092 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3093 NewR = MRI->createVirtualRegister(RC);
3098 MRI->clearKillFlags(NewR);
3106 for (MachineOperand &MO : NewMI->operands())
3129 llvm::make_early_inc_range(MRI->use_operands(FromReg)))
3153 // MIB.addMBB needs non-const pointer.
3158 // erased as "non-executable". We can't mark any new instructions
3167 // This ensures that all implicit operands (e.g. implicit-def %r31, etc)
3169 for (auto &Op : NI->operands())
3171 NI->eraseFromParent();