Lines Matching full:ed
365 ExtValue(const ExtDesc &ED) : ExtValue(ED.getOp()) {} in ExtValue()
395 OffsetRange getOffsetRange(const ExtDesc &ED) const;
406 bool replaceInstrExact(const ExtDesc &ED, Register ExtR);
407 bool replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
426 friend raw_ostream &operator<< (raw_ostream &OS, const ExtDesc &ED);
493 raw_ostream &operator<< (raw_ostream &OS, const HCE::ExtDesc &ED) { in operator <<() argument
494 assert(ED.OpNum != -1u); in operator <<()
495 const MachineBasicBlock &MBB = *ED.getOp().getParent()->getParent(); in operator <<()
499 if (ED.Rd.Reg != 0) in operator <<()
500 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); in operator <<()
503 OS << " = " << PrintExpr(ED.Expr, HRI); in operator <<()
504 if (ED.IsDef) in operator <<()
1093 // Return the allowable deviation from the current value of the extender ED,
1094 // for which the instruction corresponding to ED can be modified without
1100 OffsetRange HCE::getOffsetRange(const ExtDesc &ED) const { in getOffsetRange()
1102 // the instruction using ED will be converted to an indexed memory in getOffsetRange()
1104 unsigned IdxOpc = getRegOffOpcode(ED.UseMI->getOpcode()); in getOffsetRange()
1114 if (!ED.UseMI->mayLoad() && !ED.UseMI->mayStore()) in getOffsetRange()
1144 ExtDesc ED; in recordExtender() local
1145 ED.OpNum = OpNum; in recordExtender()
1164 ED.Rd = MI.getOperand(OpNum-1); in recordExtender()
1165 ED.IsDef = true; in recordExtender()
1172 ED.Expr.Rs = MI.getOperand(OpNum-1); in recordExtender()
1175 ED.Expr.Rs = MI.getOperand(OpNum-2); in recordExtender()
1176 ED.Expr.S = MI.getOperand(OpNum-1).getImm(); in recordExtender()
1184 ED.Rd = MI.getOperand(0); in recordExtender()
1185 ED.IsDef = true; in recordExtender()
1189 ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_hi }; in recordExtender()
1190 ED.IsDef = true; in recordExtender()
1193 ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_lo }; in recordExtender()
1194 ED.IsDef = true; in recordExtender()
1197 ED.Rd = MI.getOperand(0); in recordExtender()
1198 ED.Expr.Rs = MI.getOperand(OpNum-1); in recordExtender()
1203 ED.Expr.Rs = MI.getOperand(OpNum-1); in recordExtender()
1206 ED.Rd = MI.getOperand(0); in recordExtender()
1207 ED.Expr.Rs = MI.getOperand(OpNum+1); in recordExtender()
1208 ED.Expr.Neg = true; in recordExtender()
1211 ED.Expr.Rs = MI.getOperand(OpNum+1); in recordExtender()
1212 ED.Expr.Neg = true; in recordExtender()
1219 ED.UseMI = &MI; in recordExtender()
1222 ExtRoot ER(ED.getOp()); in recordExtender()
1230 Extenders.push_back(ED); in recordExtender()
1279 const ExtDesc &ED = Extenders[I]; in assignInits() local
1280 if (!ED.IsDef) in assignInits()
1282 ExtValue EV(ED); in assignInits()
1283 LLVM_DEBUG(dbgs() << " =" << I << ". " << EV << " " << ED << '\n'); in assignInits()
1284 assert(ED.Rd.Reg != 0); in assignInits()
1285 Ranges[I-Begin] = getOffsetRange(ED.Rd).shift(EV.Offset); in assignInits()
1290 if (ED.UseMI->getOpcode() == Hexagon::A2_tfrsi) { in assignInits()
1299 const ExtDesc &ED = Extenders[I]; in assignInits() local
1300 if (ED.IsDef) in assignInits()
1302 ExtValue EV(ED); in assignInits()
1303 LLVM_DEBUG(dbgs() << " " << I << ". " << EV << " " << ED << '\n'); in assignInits()
1304 OffsetRange Dev = getOffsetRange(ED); in assignInits()
1468 const ExtDesc &ED = Extenders[I]; in assignInits() local
1469 return ED.Expr.Rs.isSlot() == IsStack && in assignInits()
1470 ExtValue(ED).Offset == EV.Offset; in assignInits()
1498 const ExtDesc &ED = Extenders[Refs[i]]; in calculatePlacement() local
1499 MachineBasicBlock *MBB = ED.UseMI->getParent(); in calculatePlacement()
1500 RefMIs.insert(ED.UseMI); in calculatePlacement()
1606 bool HCE::replaceInstrExact(const ExtDesc &ED, Register ExtR) { in replaceInstrExact() argument
1607 MachineInstr &MI = *ED.UseMI; in replaceInstrExact()
1651 unsigned RegN = ED.OpNum; in replaceInstrExact()
1722 // Replace the extender ED with a form corresponding to the initializer ExtI.
1723 bool HCE::replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI, in replaceInstrExpr() argument
1725 MachineInstr &MI = *ED.UseMI; in replaceInstrExpr()
1854 const ExtDesc &ED = Extenders[Idx]; in replaceInstr() local
1855 assert((!ED.IsDef || ED.Rd.Reg != 0) && "Missing Rd for def"); in replaceInstr()
1857 assert(ExtRoot(ExtValue(ED)) == ExtRoot(DefV) && "Extender root mismatch"); in replaceInstr()
1860 ExtValue EV(ED); in replaceInstr()
1862 const MachineInstr &MI = *ED.UseMI; in replaceInstr()
1876 // If ED is a def, and Diff is not 0, then all uses of the register Rd in replaceInstr()
1877 // defined by ED must be in the form (Rd, imm), i.e. the immediate offset in replaceInstr()
1880 if (ED.IsDef && Diff != 0) { in replaceInstr()
1881 for (MachineOperand &Op : MRI->use_operands(ED.Rd.Reg)) { in replaceInstr()
1890 Replaced = replaceInstrExact(ED, ExtR); in replaceInstr()
1892 Replaced = replaceInstrExpr(ED, ExtI, ExtR, Diff); in replaceInstr()
1894 if (Diff != 0 && Replaced && ED.IsDef) { in replaceInstr()
1908 assert(ED.Rd.Sub == 0 && ExtR.Sub == 0); in replaceInstr()
1909 MRI->replaceRegWith(ED.Rd.Reg, ExtR.Reg); in replaceInstr()